Self-repairing Learning Rule for Spiking Astrocyte-Neuron Networks

Hill

et al. 2020

Sensors

Self Cite

The introduction of 5G communication capabilities presents additional challenges for the development of products and services that can fully exploit the opportunities offered by high bandwidth, low latency networking. This is particularly relevant to an emerging interest in the Industrial Internet of Things (IIoT), which is a foundation stone of recent technological revolutions such as Digital Manufacturing. A crucial aspect of this is to securely authenticate complex transactions between IIoT devices, whilst marshalling adversarial requests for system authorisation, without the need for a centralised authentication mechanism which cannot scale to the size needed. In this article we combine Physically Unclonable Function (PUF) hardware (using Field Programmable Gate Arrays—FPGAs), together with a multi-layer approach to cloud computing from the National Institute of Standards and Technology (NIST). Through this, we demonstrate an approach to facilitate the development of improved multi-layer authentication mechanisms. We extend prior work to utilise hardware security primitives for adversarial trojan detection, which is inspired by a biological approach to parameter analysis. This approach is an effective demonstration of attack prevention, both from internal and external adversaries. The security is further hardened through observation of the device parameters of connected IIoT equipment. We demonstrate that the proposed architecture can service a significantly high load of device authentication requests using a multi-layer architecture in an arbitrarily acceptable time of less than 1 second.

Section: Device Parameter Analysis Of Client Fpgasmentioning

confidence: 99%

“…However, in [32][33][34], the authors derive bio-inspired principles for homeostasis targeting robotic applications, where this paper emphasis the use of similar methodologies for hardware Trojan detection. Bio-inspired computing develops computational models using various models of biology.…”

Section: Device Parameter Analysis Of Client Fpgasmentioning

confidence: 99%

Hardware-Intrinsic Multi-Layer Security: A New Frontier for 5G Enabled IIoT

Al-Aqrabi

Hill

et al. 2020

Sensors

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“…In our implementation ε = 2 −6 . One aspect of our model is that it operates at an accelerated biological time scale similar to that in [16], proving to be an efficient realization of real-world tasks compared to [11].…”

Section: Hardware Implementation Of Self-learning Rulesmentioning

confidence: 99%

“…The Bienenstock, Cooper, and Munro (BCM) synaptic modification rule modulates the postsynaptic activity if it deviates from the required response [9], [10]. In this paper, we use a self-repairing learning rule [11] that uses evidence [12] to explain how the STDP and BCM learning rules co-exist to give a learning function that is under the control of postsynaptic neuron activity.…”

Section: Introductionmentioning

confidence: 99%

Fault-Tolerant Learning in Spiking Astrocyte-Neural Networks on FPGAs

2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)

Liu

Millard

et al. 2018

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Abstract-The paper presents a neuromorphic system implemented on a Field Programmable Gate Array (FPGA) device establishing fault tolerance using a learning method, which is a combination of the Spike-Timing-Dependent Plasticity (STDP) and Bienenstock, Cooper, and Munro (BCM) learning rules. The rule modulates the synaptic plasticity level by shifting the plasticity window, associated with STDP, up/down the vertical axis as a function of postsynaptic neural activity. Specifically when neurons are inactive, either early on in the normal learning phase or when a fault occurs, the window is shifted up the vertical axis (open), leading to an increase in firing rate of the postsynaptic neuron. As learning progresses, the plasticity window moves down the vertical axis until the desired postsynaptic neuron firing rate is established. Experimental results are presented to show the effectiveness of proposed approach in establishing fault tolerance. The system can maintain the network performance with at least one nonfaulty synapse. Finally, we discuss a robotic application utilizing the proposed architecture.

“…Compared to these works, the work proposed in this paper demonstrates higher fault tolerance and the methodology is feasible in the presence of at least one healthy synapse. Some recent works also suggests the use of learning mechanisms to recover faults in synapses [9], [10].…”

Section: Introductionmentioning

confidence: 99%

Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAs

2017 International Conference on Field Programmable Technology (ICFPT)

Liu

Millard

et al. 2017

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We present a novel methodology that addresses the problem of faults in synapses of a spiking neural network using astrocyte regulation, inspired by recovery processes in the brain. Since Field Programmable Gate Arrays (FPGAs) are widely used for neural network applications, we aim to achieve fault tolerance in an astrocyte-neuron unit implemented on an FPGA. A fault is considered as a reduction in transmission probability of a synapse, leading to reduced spiking activity. Our novel repair mechanism exploits Dynamic Partial Reconfiguration (DPR) of the FPGA Clock Management Tiles (CMTs) to increase the clock frequency of neurons with reduced synaptic input, which restores the firing rate to pre-fault levels. We demonstrate the repair methodology on a spiking neural network implemented on an FPGA. The system maintains effective functional behavior with a loss of up to 99% of the original synaptic inputs to a neuron. Our repair mechanism has minimal hardware overhead with the tuning circuit (repair unit) which consumes only 0.8215% of the complete design and therefore supports scalable implementations. Additionally, the overall architecture has a minimal impact on power consumption (1.371W ). The work opens up a novel way to utilize the capabilities of modern hardware to mimic homeostatic self-repair behavior achieving fault recovery.