Self-Matching SRAM With Embedded OTP Cells in Nanoscale Logic CMOS Technologies

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A thorough investigation of the parasitic resistance and capacitance (RC) effects of a single-fin FinFET on logic CMOS devices and circuits is presented. As parasitic RC effects become increasingly prominent in nanoscaled FinFET technologies, they are critical to the overall device and circuit performance. In addition, the effects of dummy patterns as well as multifin structures are analyzed and modeled in detailed. By incorporating parasitic resistance and capacitance extracted by both measurement and simulation, the static and dynamic performance characteristics of standard six transistor static random-access memory (6T-SRAM) cells are comprehensively evaluated as an example of parasitic RC effects in this investigation.

Section: Discussion On Parasitic Effects In 6t-srammentioning

confidence: 99%

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Huang¹,

Meng²,

King³

et al. 2017

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“…In general, the length of the largest square allowed is utilized to evaluate the static noise margin. [24][25][26][27] Fig. 5(a) shows the butterfly curves of the write noise margin (WNM) with and without the effect of self-heating, and Fig.…”

Section: Simulation Methodsmentioning

confidence: 99%

Self-heating effect on logic performance of 6T-SRAM based on CFET device

Zhao

Liu

et al. 2022

CFET devices have become emerging and promising candidates for continuing Moore's law at sub-3 nm nodes owing to the area advantage of the N-P stacked structure, which markedly improves the integration of circuits. However, the introduction of vertical structure leads to severe thermal issues due to the self-heating effect, resulting in the degradation of the device and circuit performance. This paper mainly evaluates and analyzes the performance of the SRAM unit built using the CFET structure. The CFET-SRAM exhibits better performance than the conventional CMOS-SRAM in terms of access delay, even with the impact of self-heating. For the multi-fin-based CFET, although the total gate capacitance increases, the enhanced current improves the static noise margin significantly. However, as the number of channels expands, sheet-based CFET devices show more comprehensive superiority of area and performance.

“…The first is the selfconverging calibration circuit, followed by a voltage follower, a ring oscillator, a buffer, and an on-chip antenna. [18][19][20][21][22][23] Following the connection of the calibration circuit, which incorporates 2D resistors and FG transistors, the resulting sense voltage, V sen , is directed into the subsequently placed voltage follower. This voltage follower serves the crucial function of stabilizing the voltage V sen passed to the ring oscillator.…”

Section: Sensing Circuit Designmentioning

confidence: 99%

Advanced self-convergent calibration for selenized two-dimensional film gas sensors

Liu,

Shen,

Wang

et al. 2024

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This research presents an innovative gas sensor system featuring a selenized 2D-film as its primary sensing material, integrated with metal-gate-coupled floating gate devices to enable self-convergent calibration. The inherent variability in resistance levels of 2D gas-sensing materials across different devices has been a significant challenge, resulting in substantial output signal deviations within the sensing circuit. To address this issue, we introduce a novel self-convergent operational technique, which effectively mitigates the impact of resistance variations, thereby enhancing the precision and reliability of gas sensing outcomes. Our proposed gas sensor system promises to deliver consistent and accurate results, even in the presence of device-to-device resistance variations, making it a valuable contribution to the field of gas sensing technology. This work holds substantial potential for various applications requiring highly accurate gas detection and quantification.