Self Checking in Current Floating-Point Units

Lipetz, Daniel; Schwarz, E.

doi:10.1109/arith.2011.18

Cited by 22 publications

(12 citation statements)

References 7 publications

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“…For the circuits using residue checking, we chose 3 or 15 as the modulus. Modulo-3 checking is used widely [10], [17], and modulo-15 checking is also used in IBM z196 microprocessor [10], [18]. We used duplication for checking of the sign bit and the exponent for all the four multipliers to evaluate error detectability and area of the significand calculation circuits fairly.…”

Section: Discussionmentioning

confidence: 99%

“…Though floating-point multipliers using full duplication achieve high capability of error detection, they have large area overhead. Reliable floating-point arithmetic units with residue checking were proposed [9] and selection of the modulus for residue checking in IBM processors was discussed in [10]. Though floating-point multipliers using residue checking can achieve high error detection ratio with smaller area overhead, they may overlook erroneous results with large magnitude of error, which is a multiple of the modulus.…”

Section: Introductionmentioning

confidence: 99%

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Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication

Kito

Akimoto

Takagi

2017

IEICE Trans. Inf. & Syst.

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SUMMARYA floating-point multiplier with concurrent error detection capability by partial duplication is proposed. It uses a truncated multiplier for checking of the significand (mantissa) multiplication instead of full duplication. The proposed multiplier can detect any erroneous output with error larger than one unit in the last place (1 ulp) of the significand, which may be overlooked by residue checking. Its circuit area is smaller than that of a fully duplicated one. Area overhead of a single-precision multiplier is about 78% and that of a double-precision one is about 65%.

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Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication

Kito

Akimoto

Takagi

2017

IEICE Trans. Inf. & Syst.

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“…As opposed to hard or permament faults, transient erros in current advanced technologies make up the main source of errors and therefore determine the failure rate of a whole chip [3]. In [4] it is shown, that concurrent error checking has been industrial practice for many years now and is absolutely necessary for high reliability systems. Thus, in order to ensure a safe operation, the multiplier has to be checked for permanent and transient errors online.…”

Section: Introductionmentioning

confidence: 98%

Concurrent Error Detection in Multipliers by Using Reduced Wordlength Multiplication and Logarithms

Uhl

Becker

2013

2013 Euromicro Conference on Digital System Design

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Checking multiplication by using logarithms has already been proposed in literature but until now it has not been used widely in practice nor have different implementations been evaluated or compared. In this paper we will analyse the error detection capability of different implementations of logarithmic checking. Based on the results we propose a new way of checking multiplication. It uses normalised and wordlength reduced operands which are multiplied by a smaller multiplier in order to estimate the result of the multiplier to be checked. The estimated result is compared to the result of the multiplier by the difference of their base 2 logarithms. This approach enables the use of inaccurate approximations for the base 2 logarithm computation and improves error detection compared to standard logarithmic checking. The error detection capability can be adjusted to the application's need for error detection by choosing the wordlength of the normalised operands. The error detection capability and the hardware overhead of this method are compared with the ones of known logarithmic checking methods.

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“…In [14] an exponent checking architecture is proposed for floating-point computations, which detects many errors but apparently it can detect fewer errors compared to the augmented design in which the mantissa is checked for errors. Similar to [13], this design is only useful for error detection.…”

Section: Related Workmentioning

confidence: 99%

“…However, the fault-tolerant floating-point arithmetic units have received less attention. In [13] a floating-point arithmetic unit with error detection capability is proposed in which a cost-efficient and complete residue checking is utilized. However, because of the utilized original method, it cannot be used for error correction.…”

Section: Related Workmentioning

confidence: 99%

A Novel Reduced-Precision Fault-Tolerant Floating-Point Multiplier

Mohajer¹,

Valinataj²

2017

IJMECS

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Abstract-This paper presents a new fault-tolerant architecture for floating-point multipliers in which the fault-tolerance capability is achieved at the cost of output precision reduction. In this approach, to achieve the faulttolerant floating-point multiplier, the hardware cost of the primary design is reduced by output precision reduction. Then, the appropriate redundancy is utilized to provide error detection/correction in such a way that the overall required hardware becomes almost the same as the primary multiplier. The proposed multiplier can tolerate a variety of permanent and transient faults regarding the acceptable reduced precisions in many applications. The implementation results reveal that the 17-bit and 14-bit mantissas are enough to obtain a floating-point multiplier with error detection or error correction, respectively, instead of the 23-bit mantissa in the IEEE-754 standardbased multiplier with a few percent area and power overheads.

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Self Checking in Current Floating-Point Units

Cited by 22 publications

References 7 publications

Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication

Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication

Concurrent Error Detection in Multipliers by Using Reduced Wordlength Multiplication and Logarithms

A Novel Reduced-Precision Fault-Tolerant Floating-Point Multiplier

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