Self-checking comparator with one periodic output

Kundu, Sandip; Sogomonyan, E.S.; Goessel, M.; Tarnick, S.

doi:10.1109/12.485577

Cited by 40 publications

(12 citation statements)

References 2 publications

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“…Therefore, a periodic self test routine is often applied to execute all resources, thus, activating dormant faults that might accumulate otherwise. The compare unit has to be self checking as in (Kundu et al, 1996), being instantiated only once. Likewise, all external components are instantiated only once, and protected by means of ECC or parity for the RAM and buses.…”

Section: Target Architecturementioning

confidence: 99%

Replicated processors on a single die – How independently do they fail?

Tummeltshammer

Steininger

2011

Elektrotech. Inftech.

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A very popular and efficient method for achieving fault tolerance is replication of components paired with a comparison of their outputs. Systems-on-chip architectures enable a cost-efficient implementation of this scheme on a single die. The resulting close physical proximity of the replica, however, implies an increased coupling, and therefore single-die solutions are more susceptible to common-cause faults (CCFs) than equivalent multi-chip approaches. Unfortunately, no answer could be given so far, to which degree the coupling decreases the dependability gain accomplished by the replication even in a single-die solution. In this paper we analyze potential coupling mechanisms and study under which circumstances they lead to identical outputs in all replica, since exactly in this case the replication and comparison scheme will fail. We perform both, simulation studies as well as comprehensive experimental investigations to derive a quantitative answer to this question. Our particular focus is on thermal effects and on the effects of disturbances in a shared power supply in a duplicated processor architecture. Beyond observing the relative probability of occurrence of CCFs, we also study the effectiveness of several countermeasures against them. We elaborate a model to decompose the genesis of CCFs into several steps, and show that very tight local and temporal coincidence of the fault effect in both replica is crucial for a CCF, which is unlikely, e.g. in the case for thermal effects. As a general result it turns out that even small asymmetries between the cores yield a drastic reduction in the CCF probability.

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Section: Target Architecturementioning

confidence: 99%

Replicated processors on a single die – How independently do they fail?

Tummeltshammer

Steininger

2011

Elektrotech. Inftech.

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“…To solve this problem additional input registers [5], additional code-preserving shift registers [14], [4], [15], additional periodic inputs [6], [8], [9], additional adder-like structures [16] and others are proposed. In general for these methods the area overhead is high, the delay may increase and in same cases the latency of error detection also increases.…”

Section: Introductionmentioning

confidence: 99%

Necessary and sufficient conditions for the existence of totally self-checking circuits

Saposhnikov¹,

Saposhnikov²,

Morozov³

et al. 2004

Proceedings. 10th IEEE International on-Line Testing Symposium

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“…Self-checking comparators and two-rail checkers are well known for their capability to detect faults present at inputs and internal nodes [16,17,18]. However, most of them target Stuck-at-fault only.…”

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confidence: 99%

A pseudo-dynamic comparator for error detection in fault tolerant architectures

Tran

Virazel

Bosio

et al. 2012

2012 IEEE 30th VLSI Test Symposium (VTS)

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Although CMOS technology scaling offers many advantages, it suffers from robustness problem caused by hard, soft and timing errors. The robustness of future CMOS technology nodes must be improved and the use of fault tolerant architectures is probably the most viable solution. In this context, Duplication/Comparison scheme is widely used for error detection. Traditionally, this scheme uses a static comparator structure that detects hard error. However, it is not effective for soft and timing errors detection due to the possible masking of glitches by the comparator itself. To solve this problem, we propose a pseudo-dynamic comparator architecture that combines a dynamic CMOS transition detector and a static comparator. Experimental results show that the proposed comparator detects not only hard errors but also small glitches related to soft and timing errors. Moreover, its dynamic characteristics allow reducing the power consumption while keeping an equivalent silicon area compared to a static comparator. This study is the first step towards a full fault tolerant approach targeting robustness improvement of CMOS logic circuits.

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Self-checking comparator with one periodic output

Cited by 40 publications

References 2 publications

Replicated processors on a single die – How independently do they fail?

Replicated processors on a single die – How independently do they fail?

Necessary and sufficient conditions for the existence of totally self-checking circuits

A pseudo-dynamic comparator for error detection in fault tolerant architectures

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