Self-checking and fail-safe LSIs by intra-chip redundancy

Kanekawa, Nobuyasu; Nohmi, Makoto; Satoh, Y.; Satoh, Hiroko

doi:10.1109/ftcs.1996.534628

Cited by 9 publications

(7 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus, the comparator has a configuration in which the prescribed alternating signals can be obtained at the outputs only when the inputs agree and the test pattern generation circuit, the fault injection circuit, and the comparator are all operating normally [12,15]. Thus, when the inputs disagree or the self-checking comparator is abnormal, the alternating signals cannot be obtained, and thus operation is fail-safe.…”

Section: A Self-checking Processor Prototypementioning

confidence: 99%

See 1 more Smart Citation

Fault detection and recovery coverage improvement by optimal clock diversity

Kanekawa¹,

Yamaguchi

Shima

2003

Systems & Computers in Japan

View full text Add to dashboard Cite

SUMMARYEnhancement of fault recovery coverage by early discovery and early recovery is indispensable in enhancing the availability of fail-safe systems and fault-tolerant systems. In clock-synchronized duplicate comparison systems, errors can be detected in the clock unit, facilitating the early discovery and recovery of faults. Addition of optimal-time diversity makes possible the prevention of error correlation in the duplicate comparison systems, which promotes coverage enhancement. This paper presents an experimental comparison of the fault detection coverage and recovery coverage of the clock-synchronized method with optimal-time diversity (the optimal clock diversity method), the clock-synchronized method without optimal-time diversity, and the loosely synchronized method. The experimental results show that the clock-synchronized method has the highest recovery coverage and that the optimal clock diversity method has the highest fault detection coverage.

show abstract

Section: A Self-checking Processor Prototypementioning

confidence: 99%

“…The authors have therefore proposed an optimal-time diversity method for a self-checking comparator designed to prevent correlated errors, and have demonstrated its effectiveness [12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Fault detection and recovery coverage improvement by optimal clock diversity

Kanekawa¹,

Yamaguchi

Shima

2003

Systems & Computers in Japan

View full text Add to dashboard Cite

show abstract

“…The former CCF can be mitigated by time diversity and the latter CCF can be mitigated by code theoretical protection as stated above. The author previously proposed a self-checking comparator with an orthogonal function and an alternate signal output [4], and an optimal time diversity to operate redundant functional blocks with time difference of half clock or its odd multiple [4]. The effect of the optimal time diversity was verified by fault injection experiments; that is, it eliminates incidence of CCFs caused by power supply noise [13], [14].…”

Section: Code-theoretical Protectionmentioning

confidence: 99%

“…In previous studies, to realize self-checking or fail-safe LSIs, on-chip redundancy (namely, redundant subsystems within a chip for detecting error), self-checking comparator and optimal time diversity techniques [4] were proposed, and a prototype LSI was fabricated [5], [6]. In addition, safety microcontrollers have been commercially launched by several vendors [7], [8].…”

Section: Introductionmentioning

confidence: 99%

Potential of Fault-Detection Coverage by means of On-Chip Redundancy - IEC61508: Are There Royal Roads to SIL 4?

Kanekawa

2013

IEICE Trans. Inf. & Syst.

View full text Add to dashboard Cite

SUMMARYThis paper investigates potential to improve faultdetection coverage by means of on-chip redundancy. The international standard on functional safety, namely, IEC61508 Ed. 2.0 Part 2 Annex E.3 prescribes the upper bound of β IC (common cause failure (CCF) ratio to all failures) is 0.25 to satisfy frequency upper bound of dangerous failure in the safety function for SIL (Safety Integrated Level) 3. On the other hand, this paper argues that the β IC does not necessarily have to be less than 0.25 for SIL 3, and that the upper bound of β IC can be determined depending on failure rate λ and CCF detection coverage. In other words, the frequency upper bound of dangerous failure for SIL3 can also be satisfied with β IC higher than 0.25 if the failure rate λ is lower than 400 [fit]. Moreover, the paper shows that on-chip redundancy has potential to satisfy SIL 4 requirement; the frequency upper bound of dangerous failure for SIL4 can be satisfied with feasible ranges of β IC , λ and CCF coverage which can be realized by redundant code.

show abstract

“…shows the configuration of the self-checking comparator[4][5]. The test pattern generator generates test patterns for each bit of the input data so that SelfSample…”

mentioning

confidence: 99%

A fail-safe microprocessor using dual synthesizable processor cores

Shimamura

Yamaguchi²,

Kanekawa³

et al.

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

Self Cite

View full text Add to dashboard Cite

A chip level redundant self-checking fail-safe microprocessor has been developed using a 0.35 pm CMOS embedded gate array. The microprocessor integrates two synthesizable processor cores and a self-checking comparator in a single chip. A full-custom processor core was transformed into each of the synthesizable cores for this purpose. Design methodologies suitable for reusing synthesizable processor cores has also been developed. Developed synthesizable processor cores and design methodologies reduce the cost of process migration of the chip. Migrating to the newer process improves the performance of the developed microprocessor with low development cost.

show abstract

Self-checking and fail-safe LSIs by intra-chip redundancy

Cited by 9 publications

References 1 publication

Fault detection and recovery coverage improvement by optimal clock diversity

Fault detection and recovery coverage improvement by optimal clock diversity

Potential of Fault-Detection Coverage by means of On-Chip Redundancy - IEC61508: Are There Royal Roads to SIL 4?

A fail-safe microprocessor using dual synthesizable processor cores

Contact Info

Product

Resources

About