'Self-body-biased' SOI MOSFET through 'depletion isolation effect'

Abstract

In its 'ON' state its body potential is electrically isolated from the external body terminal by the gate depletion layer, and is controlled automatically through the drain current and drain voltage. More than 30 % improvement in current drivability is predicted.

Selectable Logarithmic/Linear Response Active Pixel Sensor Cell with Reduced Fixed-Pattern-Noise Based on Dynamic Threshold MOS Operation

“…In addition to the functionality of M4, those of M1 through M3 are the same as those previously reported. 3) In the linear response operation the V th of M1 determines the reset voltage of the photodiode; M2 is a source follower amplifier; M3 functions as a data selector. The V th of M1 and the V th and/or I d of M2 are the major origins of FPN of APS circuits.…”

“…1,2) The FPN can be suppressed using the commonly used correlated double sampling (CDS) technique in CMOS APS array devices, but additional external circuitry is required. 1,2) One of the authors proposed a novel APS with reduced FPN utilizing dynamic threshold MOSFETs (DTMOSs) and demonstrated the possibility of FPN reduction 3) using a DTMOS with an inherently suppressed threshold voltage and/or drain conductance fluctuation 4) compared with a bulk counterpart without using the CDS technique.…”

“…In this paper the authors propose a new APS cell with a selectable logarithmic/linear response, which can be used to achieve reduced FPN without requiring additional FPN suppression circuitry. In addition to the three DTMOSs used in our previous study, 3) the newly proposed APS cell utilizes another DTMOS that is responsible for a logarithmic current-voltage conversion functionality. Since DTMOS has an ideal subthreshold slope (S) in its weak inversion region that is theoretically independent of all device parameters such as gate oxide thickness, channel width and channel length, as will be described in §3, the resulting logarithmic current-voltage conversion functionality should also be ideal.…”

Feasibility Study of a Novel Four Transistor Silicon-on-Insulator Static Random Access Memory Cell Utilizing Partial Trench Isolation

“…One of the candidate device structures for such applications is the ''selfbody-biased'' (''SBB'') silicon-on-insulator (SOI) metaloxide-semiconductor field-effect transistor (MOSFET), which utilizes the expansion of the gate depletion layer beneath the auxiliary ''T-shaped'' gate electrode in order to modulate the body potential, thus enhancing its current drivability in the ''ON'' state. [1][2][3] By further modifying the gate electrode shape, the author has already proposed the ''SBB'' static random access memory (SRAM) cell operating at 0.5 V. 4,5) However this ''SBB'' SRAM cell has limited layout flexibility because it inevitably requires the ''Hshaped'' gate electrodes for realizing the cross-coupled inverter pair of the SRAM cell.…”