Self-authenticating secure boot for FPGAs

Pocklassery, Goutham; Che, Wenquan; Saqib, Fareena; Areno, Matthew; Plusquellic, Jim

doi:10.1109/hst.2018.8383919

Cited by 9 publications

(7 citation statements)

References 7 publications

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“…The authors specify that their solution should be implemented with the PUF into a single chip (ASIC) in order to prevent an attacker from obtaining the PUF response by sniffing the SPI bus. In the same way, the approach of Pocklassery et al [132] uses the output of a PUF, implemented into a System-on-Chip (SoC), as a decryption key. This approach integrates the PUF and the rest of the security module into the same chip and is therefore not vulnerable to the previous attack.…”

Section: ) Platform Independentmentioning

confidence: 99%

Firmware Integrity Protection: A Survey

Marchand,

Imine,

Ouarnoughi

et al. 2023

IEEE Access

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Over the last years, firmware integrity protection has significantly been addressed in various contexts such as internet of things, vehicles, wireless sensor networks and other systems. However, due to variety of studied systems, the proposed approaches often make divergent and sometimes even conflicting security assumptions. In this regard, we propose in this article a complete survey of the most relevant approaches addressing the firmware integrity protection regardless the considered system or field of application. We first organize the approaches in three main categories, depending on the protection type: 1. secure update, 2. attestation, and 3. secure boot. We then propose two new taxonomies, the first one concerns secure update mechanisms and the second one considers secure boot. Moreover, we extend the scope of an existing taxonomy for attestation mechanisms by studying new approaches and discussing limitations. Finally, we identify open research challenges and then give suggestions and guidelines on how to address them.

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Section: ) Platform Independentmentioning

confidence: 99%

Firmware Integrity Protection: A Survey

Marchand,

Imine,

Ouarnoughi

et al. 2023

IEEE Access

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“…DPR-based approaches (e.g., [22,23]) suggest dividing the Programmable Logic (PL) fabric into two zones, the static/security partition and the application partition. The security partition implements functions required for authentication of the device, e.g., a PUF.…”

Section: Secure Boot In Fpgasmentioning

confidence: 99%

Secure Boot for Reconfigurable Architectures

2020

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Reconfigurable computing is becoming ubiquitous in the form of consumer-based Internet of Things (IoT) devices. Reconfigurable computing architectures have found their place in safety-critical infrastructures such as the automotive industry. As the target architecture evolves, it also needs to be updated remotely on the target platform. This process is susceptible to remote hijacking, where the attacker can maliciously update the reconfigurable hardware target with tainted hardware configuration. This paper proposes an architecture of establishing Root of Trust at the hardware level using cryptographic co-processors and Trusted Platform Modules (TPMs) and enable over the air updates. The proposed framework implements a secure boot protocol on Xilinx based FPGAs. The project demonstrates the configuration of the bitstream, boot process integration with TPM and secure over-the-air updates for the hardware reconfiguration.

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“…DPR based approaches, such as [21] and [22], suggest dividing the Programmable Logic (PL) fabric into two zones, the static / security partition and the application partition. The security partition implements functions required for authentication of the device, e.g.…”

Section: Secure Boot In Fpgasmentioning

confidence: 99%

Secure Boot for Reconfigurable Architectures

Siddiqui¹,

Gui²,

Saqib³

2020

Preprint

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Reconfigurable computing is becoming ubiquitous in the form of consumer-based Internet of Things (IoT) devices. Reconfigurable computing architectures have found their place in safety-critical infrastructures such as the automotive industry. As the target architecture evolves, it also needs to be updated remotely on the target platform. This process is susceptible to remote hijacking, where the attacker can maliciously update the reconfigurable hardware target with tainted hardware configuration. This paper proposes an architecture of establishing Root of Trust at the hardware level using cryptographic co-processors and Trusted Platform Modules (TPMs) and enable over the air updates. The proposed framework implements secure boot protocol on Xilinx based FPGAs. The project demonstrates the configuration of the bitstream, boot process integration with TPM and secure over-the-air updates for the hardware reconfiguration.

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Self-authenticating secure boot for FPGAs

Cited by 9 publications

References 7 publications

Firmware Integrity Protection: A Survey

Firmware Integrity Protection: A Survey

Secure Boot for Reconfigurable Architectures

Secure Boot for Reconfigurable Architectures

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