Self-Alignment with Copper Pillars Micro-Bumps for Positioning Optical Devices at Submicronic Accuracy

Zonou, Yezouma D; Bernabé, Stéphane; Fowler, Daivid; Francou, Mireille; Castany, Olivier; Arguel, Philippe

doi:10.1109/ectc.2017.234

Cited by 6 publications

(4 citation statements)

References 7 publications

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“…In this configuration, angle tolerances should be kept below 0.2°, and the absolute position of the lens towards the VGC and the optical fiber core below 1 µm. This range of tolerance can be obtained by using self-alignment approaches, as described in [158].…”

Section: Fiber Packagingmentioning

confidence: 99%

“…The in-plane edge butt coupling technique requires 1-2 µm tolerance between the output mode of the fiber and the PIC coupler for a output mode size diameter of 8µm. By using metamaterial based edge couplers, Barwicz et al [159] demonstrated coupling losses of 0.7 dB (TEmode) 1.4 dB (TM mode) between the PIC and an optical fiber. This metamaterial edge coupler , acting as a Spot Size Converter (SSC) enables the use of self-alignment techniques such as etching V-grooves in the PIC substrate to allow self positioning of a flat cleaved fiber at the end of the taper.…”

Section: Fiber Packagingmentioning

confidence: 99%

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Silicon photonics for terabit/s communication in data centers and exascale computers

Bernabé

Wilmart

Hasharoni³

et al. 2021

Solid-State Electronics

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Section: Fiber Packagingmentioning

confidence: 99%

Section: Fiber Packagingmentioning

confidence: 99%

Silicon photonics for terabit/s communication in data centers and exascale computers

Bernabé

Wilmart

Hasharoni³

et al. 2021

Solid-State Electronics

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“…The experimental self-alignment of Cu µ-pillars (also called C2 bumps) and standard ball grid array joints (called C4 bumps) has been shown on numerous occasions to exhibit a final misalignment of less than 1 µm following bonding. [9][10][11][12][13][14][15][16][17][18] Through this assembly mechanism, the need for active alignment of optical components can be significantly reduced or eliminated. This is crucial because active alignment increases fabrication time and the overall package cost, which already accounts for over 80% of the total expense for photonic packages.…”

Section: Introductionmentioning

confidence: 99%

High density vertical optical interconnects for passive assembly

Weninger

Otálvaro²,

Jain³

et al. 2023

Optical Interconnects XXIII

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The co-packaging of optics and electronics provides a potential path forward to achieving beyond 50 Tbps top of rack switch packages. In a co-packaged design, the scaling of bandwidth, cost, and energy is governed by the number of optical transceivers (TxRx) per package as opposed to transistor shrink. Due to the large footprint of optical components relative to their electronic counterparts, the vertical stacking of optical TxRx chips in a co-packaged optics design will become a necessity. As a result, development of efficient, dense, and wide alignment tolerance chip-to-chip optical couplers will be an enabling technology for continued TxRx scaling. In this paper, we propose a novel scheme to vertically couple into standard 220 nm silicon on insulator waveguides from 220 nm silicon nitride on glass waveguides using overlapping, inverse double tapers. Simulation results using Lumerical’s 3D Finite Difference Time Domain solver are presented, demonstrating insertion losses below -0.13 dB for an inter-chip spacing of 1 μm; 1 dB vertical and lateral alignment tolerances of approximately 2.6 μm and ± 2.8 μm, respectively; a greater than 300 nm 1 dB bandwidth; and 1 dB twist and tilt tolerances of approximately ± 2.3 degrees and 0.4 degrees, respectively. These results demonstrate the potential of our coupler for use in co-packaged designs requiring high performance, high density, CMOS compatible out of plane optical connections.

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“…The passive self-alignment occurs due to the surface tension of the molten Sn-Ag-Cu (SAC) cap which sits atop the Cu 𝜇-pillar joint. The experimental self-alignment of Cu 𝜇-pillars (also called C2 bumps) and standard ball grid array joints (called C4 bumps) has been shown on numerous occasions to exhibit a final misalignment of less than 1 𝜇m following bonding [9][10][11][12][13][14][15][16][17][18]. Through this assembly mechanism, the need for active alignment of optical components can be significantly reduced or eliminated.…”

Section: Introductionmentioning

confidence: 99%

High Density Vertical Optical Interconnects for Passive Assembly

Weninger¹,

Serna²,

Jain³

et al. 2022

Preprint

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The co-packaging of optics and electronics provides a potential path forward to achieving beyond 50 Tbps top of rack switch packages. In a co-packaged design, the scaling of bandwidth, cost, and energy is governed by the number of optical transceivers (TxRx) per package as opposed to transistor shrink. Due to the large footprint of optical components relative to their electronic counterparts, the vertical stacking of optical TxRx chips in a co-packaged optics design will become a necessity. As a result, development of efficient, dense, and wide alignment tolerance chip-to-chip optical couplers will be an enabling technology for continued TxRx scaling. In this paper, we propose a novel scheme to vertically couple into standard 220 nm silicon on insulator waveguides from 220 nm silicon nitride on glass waveguides using overlapping, inverse double tapers. Simulation results using Lumerical's 3D Finite Difference Time Domain solver solver are presented, demonstrating insertion losses below -0.13 dB for an inter-chip spacing of 1 𝜇m, 1 dB vertical and lateral alignment tolerances of approximately ± 2.7 𝜇m, a greater than 300 nm 1 dB bandwidth, and 1 dB twist and tilt tolerance of approximately 2.3 degrees and 0.4 degrees, respectively. These results demonstrate the potential of our coupler for use in co-packaged designs requiring high performance, high density, CMOS compatible out of plane optical connections.

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Self-Alignment with Copper Pillars Micro-Bumps for Positioning Optical Devices at Submicronic Accuracy

Cited by 6 publications

References 7 publications

Silicon photonics for terabit/s communication in data centers and exascale computers

Silicon photonics for terabit/s communication in data centers and exascale computers

High density vertical optical interconnects for passive assembly

High Density Vertical Optical Interconnects for Passive Assembly

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