Self-Aligned Top-Gate Amorphous InGaZnO TFTs With Plasma Enhanced Chemical Vapor Deposited Sub-10 nm SiO<sub>2</sub> Gate Dielectric for Low-Voltage Applications

Zhang, Yuqing; Yang, Huan; Peng, Hao; Cao, Yunkai; Qin, Lu; Zhang, Shengdong

doi:10.1109/led.2019.2931358

Cited by 29 publications

(19 citation statements)

References 26 publications

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“…This variation in the low-frequency regime is attributed to hydroxyl-related defects, which increase capacitance by causing charge polarization . However, the capacitance change in our SiO 2 film without O 2 in the low-frequency regime was less than 2%, which is still considerably lower than that obtained in previous studies (more than 10%). , Thus, both sputtered SiO 2 films with and without O 2 contained few hydroxyl-related defects.…”

Section: Results and Discussioncontrasting

confidence: 71%

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Low-Temperature Fabrication (≤150 °C) of High-Quality Sputtered Silicon Oxide Thin Film with Hydrogen Plasma Treatment

Seo

Park

Jeon

et al. 2020

ACS Appl. Electron. Mater.

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Low-temperature fabrication of thin-film dielectrics is essential for various applications including flexible/stretchable electronics, monolithic threedimensional integrated circuits, and large-area sensors/displays. Silicon dioxide is one of the most extensively used dielectric materials, but conventional deposition methods such as plasma-enhanced chemical vapor deposition and atomic layer deposition require relatively high temperatures. In this study, a high-quality SiO 2 thin film was fabricated at low temperatures below 150 °C using sputtering and hydrogen plasma treatment. The sputtered SiO 2 thin film exhibited low leakage current (3 × 10 −7 A/cm 2 at 3 MV/cm) and a high breakdown field (11.33 MV/ cm). After hydrogen plasma treatment was carried out under optimized conditions, the interface trap density between Si and sputtered SiO 2 was minimized to 7 × 10 11 cm −2 eV −1 , which is comparable to the corresponding value for thermally grown SiO 2 . The results of X-ray photoelectron spectroscopy and secondary-ion mass spectroscopy confirmed that the hydrogen treatment effectively passivates dangling bonds and reduces the portion of oxygen-deficient species.

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Section: Results and Discussioncontrasting

confidence: 71%

“…30 However, the capacitance change in our SiO 2 film without O 2 in the low-frequency regime was less than 2%, which is still considerably lower than that obtained in previous studies (more than 10%). 30,31 Thus, both sputtered SiO 2 films with and without O 2 contained few hydroxyl-related defects.…”

Section: ■ Results and Discussionmentioning

confidence: 95%

Low-Temperature Fabrication (≤150 °C) of High-Quality Sputtered Silicon Oxide Thin Film with Hydrogen Plasma Treatment

Seo

Park

Jeon

et al. 2020

ACS Appl. Electron. Mater.

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“…(a) Mobility vs subthreshold slope (SS) of literature top-gate IGZO TFTs for various dielectric materials. ,,,− (b) Mobility vs SS for IGZO TFTs with solution-processed dielectrics. The circular symbols represent linear mobilities.…”

Section: Resultsmentioning

confidence: 99%

Self-Assembled Nanodielectrics for Solution-Processed Top-Gate Amorphous IGZO Thin-Film Transistors

Stallings

Smith

Chen

et al. 2021

ACS Appl. Mater. Interfaces

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Metal oxide semiconductors, such as amorphous indium gallium zinc oxide (a-IGZO), have made impressive strides as alternatives to amorphous silicon for electronics applications. However, to achieve the full potential of these semiconductors, compatible unconventional gate dielectric materials must also be developed. To this end, solution-processable self-assembled nanodielectrics (SANDs) composed of structurally well-defined and durable nanoscopic alternating organic (e.g., stilbazolium) and inorganic oxide (e.g., ZrO x and HfO x ) layers offer impressive capacitances and low processing temperatures (T ≤ 200 °C). While SANDs have been paired with diverse semiconductors and have yielded excellent device metrics, they have never been implemented in the most technologically relevant top-gate thin-film transistor (TFT) architecture. Here, we combine solution-processed a-IGZO with solution-processed four-layer Hf-SAND to fabricate top-gate TFTs, which exhibit impressive electron mobilities (μ SAT = 19.4 cm 2 V −1 s −1 ) and low threshold voltages (V th = 0.83 V), subthreshold slopes (SS = 293 mV/dec), and gate leakage currents (10 −10 A) as well as high bias stress stability.

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“…[ 10,11 ] As a result, poor subthreshold swing (SS), larger power consumption, and inferior stability are commonly observed in BCE TFTs, which is unfavorable for the advanced display applications. [ 12–14 ] The evolution of next‐generation displays and flexible electronics requires higher resolution and faster switching speed, further strengthening the demand for improving carrier mobility, enhancing gate control ability, and lowering working voltage. [ 15,16 ] Thus, it is imperative to explore new structure for TFTs to satisfy the ever‐increasing requirements.…”

Section: Introductionmentioning

confidence: 99%

Self‐Alignment Embedded Thin‐Film Transistor with High Transparency and Optimized Performance

Zheng

et al. 2022

Adv Materials Technologies

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Amorphous oxide semiconductor thin‐film transistors (AOS TFTs) have shown significant potential in the applications of increasingly advanced transparent and flexible electronic devices, where high speed, high transparency, and low power consumption are highly demanded. Yet, typical back‐channel etch (BCE) configuration used in the majority of TFTs still suffers from poor gate controllability, severe electrical field dispersion, relatively large parasitic capacitance and contact resistance. Here, a new embedded structure for TFTs with self‐alignment and even simpler fabrication process, outperforming conventional BCE counterpart in above aspects, is proposed in this work. More concentrated electrical field, improved gate control ability accompanied with lower contact resistance are achieved in the embedded TFTs. Consequently, superior electrical characteristics with subthreshold swing of 106.7 mV dec−1 and mobility as high as 32.10 cm2 V−1 s−1 are obtained. In addition, leakage current as well as contact resistance evidently decline compared to that in traditional BCE TFTs. By the assistance of Silvaco TCAD simulation, the performance and mechanism behind are cross‐validated from another perspective. Overall, such embedded configuration has equipped TFTs with appealing performance and it is also possible to enable other devices exploiting such structure with new possibility and thus a broader application.

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Self-Aligned Top-Gate Amorphous InGaZnO TFTs With Plasma Enhanced Chemical Vapor Deposited Sub-10 nm SiO₂ Gate Dielectric for Low-Voltage Applications

Cited by 29 publications

References 26 publications

Low-Temperature Fabrication (≤150 °C) of High-Quality Sputtered Silicon Oxide Thin Film with Hydrogen Plasma Treatment

Low-Temperature Fabrication (≤150 °C) of High-Quality Sputtered Silicon Oxide Thin Film with Hydrogen Plasma Treatment

Self-Assembled Nanodielectrics for Solution-Processed Top-Gate Amorphous IGZO Thin-Film Transistors

Self‐Alignment Embedded Thin‐Film Transistor with High Transparency and Optimized Performance

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Self-Aligned Top-Gate Amorphous InGaZnO TFTs With Plasma Enhanced Chemical Vapor Deposited Sub-10 nm SiO2 Gate Dielectric for Low-Voltage Applications

Cited by 29 publications

References 26 publications

Low-Temperature Fabrication (≤150 °C) of High-Quality Sputtered Silicon Oxide Thin Film with Hydrogen Plasma Treatment

Low-Temperature Fabrication (≤150 °C) of High-Quality Sputtered Silicon Oxide Thin Film with Hydrogen Plasma Treatment

Self-Assembled Nanodielectrics for Solution-Processed Top-Gate Amorphous IGZO Thin-Film Transistors

Self‐Alignment Embedded Thin‐Film Transistor with High Transparency and Optimized Performance

Contact Info

Product

Resources

About

Self-Aligned Top-Gate Amorphous InGaZnO TFTs With Plasma Enhanced Chemical Vapor Deposited Sub-10 nm SiO₂ Gate Dielectric for Low-Voltage Applications