Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation

Kobayashi, T.; Sakurai, Takayasu

doi:10.1109/cicc.1994.379721

Cited by 76 publications

(26 citation statements)

References 2 publications

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“…It was introduced for improving energy efficiency, by reclaiming performance lost to margins due to variations [21]- [30]. Liu et al [31] showed that body biasing is very effective to balance the nMOS and pMOS for achieving higher SNM's in ultra-thin body and BOX (UTBB) devices.…”

Section: Upsizing Length (Unconventional Sizing)mentioning

confidence: 99%

Using body bias when upsizing length for maximizing the static noise margins of CMOS gates

Kharbash

Beiu

Tache

et al. 2013

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

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This paper uses body bias for improving on a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). The method leads to highly reliable gates, operating correctly over the whole voltage range. Besides calculating the threshold voltage (V th ) exactly (precise L's) and having more accurate SNMs (maximum square method), in this paper we shall use biasing (V bs ) for having a single L opt for all transistors (as opposed to having two different L opt , one for nMOS and another one for pMOS) leading to better manufacturability. Simulations for INV, NAND-2, and NOR-2 show that although V th and L change by ~10%, by using V bs we can still achieve very high SNM's, while additionally reducing power and energy to ~50%.

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Section: Upsizing Length (Unconventional Sizing)mentioning

confidence: 99%

Using body bias when upsizing length for maximizing the static noise margins of CMOS gates

Kharbash

Beiu

Tache

et al. 2013

2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS)

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“…Although there are some leakage monitors had been proposed already [6][7][8], they miss GIDL effect. For example, Ioff_s is enhanced by slight gate voltage to detection [6].…”

Section: Optimal Vbb Scan Under Gidl Effectmentioning

confidence: 99%

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

Fujii

Suzuki

Notani

et al. 2008

ESSCIRC 2008 - 34th European Solid-State Circuits Conference

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This paper proposes on-chip leakage monitor circuit to scan optimal reversed body-biasing voltage (VBB) at which leakage current becomes minimal under gate induced drain leakage (GIDL) effect. The proposed circuit determines optimal VBB from the differential measurement of two replica circuit without absolute leakage current measurement. We fabricated this leakage monitor circuit in a 45nm-CMOS process. Measurement results shows 0.1 V resolution of VBB optimization.

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“…Recently, efforts to reduce power (and energy) consumption have seen considerable work at transistor/gate level with researchers seeking to adaptively control the body bias, and performing operations in weak inversion (also known as subthreshold, i.e., with V DD < V th ) [22], [23], [24]. In this tutorial we will review such methods and summarize their potential.…”

Section: Introductionmentioning

confidence: 99%

Femto Joule Switching for Nano Electronics

Beiu

Nyathi

Aunet

et al. 2006

IEEE International Conference on Computer Systems and Applications, 2006.

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Advancement in silicon technology has led to miniaturization of devices, scaled power supply voltages and faster transistor switching speeds just to name a few. Along with these improvements came issues such as threshold voltage scaling, interconnect delays, sensitivity to variations, and increased power dissipation. Device miniaturization has also seen a rise of battery-operated electronic devices with very stringent energy requirements. Clearly, power dissipation is already a major design challenge in highly integrated systems. Leakage currents are becoming significant as the power supply and threshold voltages are scaled. Low power/energy techniques are thus very critical. This tutorial will review known techniques for reducing power/energy, focusing on recent results scaling the supply and the device threshold voltages and on bridging the divide between strong and weak inversion operations, as well as on using emerging nanoelectronic devices. These will show that GHz frequencies could be sustained in the (sub-)femto Joule per inverter energy range.

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Self-adjusting threshold-voltage scheme (SATS) for low-voltage high-speed operation

Cited by 76 publications

References 2 publications

Using body bias when upsizing length for maximizing the static noise margins of CMOS gates

Using body bias when upsizing length for maximizing the static noise margins of CMOS gates

On-chip leakage monitor circuit to scan optimal reverse bias voltage for adaptive body-bias circuit under gate induced drain leakage effect

Femto Joule Switching for Nano Electronics

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