Selective triple Modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs

Samudrala, P.K.; Ramos, J.; Katkoori, Srinivas

doi:10.1109/tns.2004.834955

Cited by 167 publications

(79 citation statements)

References 15 publications

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“…However, designing such a computer is much more complex. Its intricate design increases the design cost and introduces more faults [28][29][30][31]. In conclusion, all the above hardware-based redundancy approaches can only protect a system against one processor failure, thus these are only limited to dealing with a single failure.…”

Section: Redundancy Schemesmentioning

confidence: 99%

Survey and future directions of fault-tolerant distributed computing on board spacecraft

Fayyaz

Vladimirova

2016

Advances in Space Research

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Current and future space missions demand highly reliable on-board computing systems, which are capable to carry out high-performance data processing. At present no single computing scheme could efficiently tackle high-performance computing as well as reliability. This paper aims to address that gap. In the first part of the paper, a detailed survey of fault-tolerant distributed computing systems for space applications is presented. Fault types and performance parameters for assessment of a fault-tolerant system are introduced. Redundancy schemes for distributed systems are analysed. A review of the state-of-the-art on fault-tolerant distributed systems is presented and limitations of current approaches are discussed. In the second part of the paper, a new fault-tolerant distributed computing platform with wireless links among the computing nodes is proposed. Novel algorithms, enabling important aspects of the architecture, such as time slot priority adaptive fault-tolerant channel access and fault-tolerant distributed computing using task migration are introduced.

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Section: Redundancy Schemesmentioning

confidence: 99%

Survey and future directions of fault-tolerant distributed computing on board spacecraft

Fayyaz

Vladimirova

2016

Advances in Space Research

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“…This includes a wide variety of solutions based on: Error Detection and Correction Codes -EDACs [18], gate-level logic redundancy [19,20], and architectural level protection [21]. More recent techniques propose selective hardening of the system, adding protection only to the most vulnerable hardware parts [22]; or reducing the performance degradation by applying partial redundant threading [23,24].…”

Section: Related Workmentioning

confidence: 99%

“…They propose to transfer to the software world the concept of selective hardening, typical from the hardware world [22,39,40]. In [15,16], the authors propose the selective instruction replication to guarantee the application-level correctness in multimedia applications.…”

Section: Related Workmentioning

confidence: 99%

Selective SWIFT-R

et al. 2013

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Commercial off-the-shelf microprocessors are the core of low-cost embedded systems due to their programmability and cost-effectiveness. Recent advances in electronic technologies have allowed remarkable improvements in their performance. However, they have also made microprocessors more susceptible to transient faults induced by radiation. These non-destructive events (soft errors), may cause a microprocessor to produce a wrong computation result or lose control of a system with catastrophic consequences. Therefore, soft error mitigation has become a compulsory requirement for an increasing number of applications, which operate from the space to the ground level. In this context, this paper uses the concept of selective hardening, which is aimed to design reduced-overhead and flexible mitigation techniques. Following this concept, a novel flexible version of the software-based fault recovery technique known as SWIFT-R is proposed. Our approach makes possible to select different registers subsets from the microprocessor register file to be protected on software. Thus, design space is enriched with a wide spectrum of new partially protected versions, which offer more flexibility to designers. This permits to find the best tradeoffs between performance, code size, and fault coverage. Three case studies have been developed to show the applicability and flexibility of the proposal.

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“…It requires the triplication of all architectural elements along with a voter, thus demanding considerable amounts of resources. Attempts were made in [38] to reduce the costs associated with fault mitigation by only applying TMR to the most critical components of a design.…”

Section: Related Workmentioning

confidence: 99%

Efficient fault tolerant SHA-2 hash functions for space applications

Juliato

Gebotys

Elbaz

2009

2009 IEEE Aerospace Conference

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Abstract-Satellites are extensively used by public and private sectors to support a variety of services. Considering the cost and the strategic importance of these spacecrafts, it is fundamental to utilize strong cryptographic primitives to assure their security. However, it is of utmost importance to consider fault tolerance in their designs due to the harsh environment found in space, while keeping low area and power consumption. Therefore, this paper proposes novel fault tolerant schemes for the SHA-2 family of hash functions and analyzes their resistance to SEUs. Results obtained through FPGA implementation show that our best fault tolerant scheme for SHA-512 uses up to 32% less area and consumes up to 43% less power than the commonly used TMR technique. Moreover, its memory and registers are 435 and 175 times more resistant to SEUs than TMR. These results are crucial for supporting low area and low power fault tolerant cryptographic primitives in satellites.

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Selective triple Modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs

Cited by 167 publications

References 15 publications

Survey and future directions of fault-tolerant distributed computing on board spacecraft

Survey and future directions of fault-tolerant distributed computing on board spacecraft

Selective SWIFT-R

Efficient fault tolerant SHA-2 hash functions for space applications

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