SEL/SEU/SEFI/TID Results of the Radiation Hardened DDR3 SDRAM Memory Solution

Wang, Pierre-Xiao; Köhler, P.; Herrmann, Martin; Fichna, T.; Pouget, Vincent; Saigné, Frédéric

doi:10.1109/nsrec.2018.8584290

Cited by 3 publications

(1 citation statement)

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“…Considering that the memory management unit (MMU) is responsible for translation between the virtual address, computed and processed by the PS, and the physical address. As an effect of SEU/MBU in MMU, a virtual address can be translated to the wrong physical address, leading to the PS to request for a physical address with the content of 0 [20].…”

Section: Clear Content In the Memorymentioning

confidence: 99%

Analysis of Single Event Effects on Embedded Processor

et al. 2021

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The continuous scaling of electronic components has led to the development of high-performance microprocessors which are even suitable for safety-critical applications where radiation-induced errors, such as single event effects (SEEs), are one of the most important reliability issues. This work focuses on the development of a fault injection environment capable of analyzing the impact of errors on the functionality of an ARM Cortex-A9 microprocessor embedded within a Zynq-7000 AP-SoC, considering different fault models affecting both the system memory and register resources of the embedded processor. We developed a novel Python-based fault injection platform for the emulation of radiation-induced faults within the AP-SoC hardware resources during the execution of software applications. The fault injection approach is not intrusive, and it does not require modifying the software application under evaluation. The experimental analyses have been performed on a subset of the MiBench benchmark software suite. Fault injection results demonstrate the capability of the developed method and the possibility of evaluating various sets of fault models.

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Section: Clear Content In the Memorymentioning

confidence: 99%