SEE evaluation of ARM M0 cores in a 28 nm FDSOI technology

Shi, Shuting; Liu, R.; Evans, Adrian; Li, X.-T.; Zheng, Yulong; Chen, Li; Glorieux, Maximilien; Sánchez, Ángel; Wong, Rick; Wen, Shi-Jie; Cunha, J. P. C.; Guo, Gang; Ferlet-Cavrois, V.; Summerer, Leopold; Entrena, Luis

doi:10.1016/j.microrel.2021.114214

Cited by 1 publication

(1 citation statement)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…An erroneous change of the state held in a storage cell caused by a particle strike is called Single event upset (SEU), which is the key contributor to the overall system soft error rate in modern VLSI circuits [4]. The SEU robustness of flip-flops is essential to ensure the overall reliability since flip-flop is one of the major elements in many digital designs [5,6]. Radiation Hardening by Design (RHBD) is an important technique to mitigate SEU in flip-flops as it works in commercial CMOS technology with no violation of design rules.…”

Section: Introductionmentioning

confidence: 99%

A low power consumption and cost-efficient SEU-tolerant pulse-triggered flip-flop design

Jin

Zhang

et al. 2021

IEICE Electron. Express

View full text Add to dashboard Cite

A power-efficient Single Event Upset (SEU) -tolerant pulsetriggered flip-flop design is presented. The dual-modular redundant design takes advantage of concise formation of pulse-triggered designs, and avoids the disadvantages of it, such as high power consumption. Clock-gating scheme is applied to reduce power consumption. The static configuration and the avoidance of contention mechanism led to the balance of power consumption, speed and SEU tolerance. The SEU tolerance is evaluated by means of SEU cross section, which is significantly lower than conventional D flip-flop. The proposed flip-flop is designed in 55nm CMOS technology to evaluate performances. The proposed design achieves the lowest power consumption, which is even lower than conventional D flip-flop. Although the speed is sacrificed, the lowest power-delay product is achieved among hardened designs. The proposed design provides solution to speedinsensitive and power-constrained applications.

show abstract

Section: Introductionmentioning

confidence: 99%