SEE characteristics of small feature size devices by using laser backside testing

Gao, Feng; Shipeng, Shangguan; Ma, Y.; Han, Ju‐Guang

doi:10.1088/1674-4926/33/1/014008

Cited by 3 publications

(2 citation statements)

References 20 publications

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“…The technical specifications of the PPLSEE-1 are shown in Table 1. PPLSEE-1 achieves precise positioning of SEFI-sensitive areas through controlling the movement of the Device Under Test (DUT) through a highprecision three-dimensional moving platform [20][21][22]. We have developed a testing system for investigating the SEFI of ADCs, which is illustrated in Figure 1.…”

Section: Methodsmentioning

confidence: 99%

Experiment Study of Single Event Functional Interrupt in Analog-to-Digital Converters Using a Pulsed Laser

Mai

Zhu

et al. 2023

Electronics

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Single Event Functional Interrupt (SEFI) poses a severe threat to the normal operation of spacecraft. This paper investigates SEFI in Analog-to-Digital Converters (ADCs) with storage units using precision positioning of pulsed lasers. Based on the experiment, it was discovered that a bit flip in the configuration registers in ADCs results in changes in parameters such as digital filter frequency, operating mode, and gain, leading to an upward or downward offset of ADC output codes. Similarly, a bit flip in the calibration registers also causes ADC output codes to shift upwards or downwards, or even output a value of zero. Furthermore, it was observed that SEFI phenomena can occur due to current latch-up in ADC input pins, causing the inability to read or write data in ADC storage units. This current latch-up can be resolved through power cycling or configuring the pins into a high-impedance state. This work highlights the significance of SEFI phenomena in ADCs, emphasizing the serious threat posed by storage unit flipping-induced SEFI to the proper functioning of ADCs. Moreover, the SEFI phenomenon caused by current latch-up in input pins is difficult to detect in practice, making it highly elusive. Once it occurs, it severely impacts the functionality of ADCs.

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Section: Methodsmentioning

confidence: 99%

Experiment Study of Single Event Functional Interrupt in Analog-to-Digital Converters Using a Pulsed Laser

Mai

Zhu

et al. 2023

Electronics

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“…Figure 4 shows a schematic diagram of the pulsed laser unit. The laser setup consists of the component laser generator, the optical path system, the 3D mobile table, the synchronization control system and the host computer [40][41][42]. Table 1 shows the main parameters of the laser equipment.…”

Section: Experimental Setup and Devices Selectionmentioning

confidence: 99%

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Xin

Zhu

et al. 2023

Electronics

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Bulk silicon Complementary Metal Oxide Semiconductor (CMOS) devices have distinct single event latch-up (SEL) problems in aerospace. Therefore, it is essential that CMOS devices are designed with appropriate circuit-level methods. Traditional resistor hardness satisfies the current aerospace trend of low cost, high performance, and miniaturization. Therefore conventional resistor hardness is often applied in circuit-level designs due to the reduction of latch-up current. In circuits containing a DC-DC buck converter, the resistor is connected to the back of the converter in the traditional method. However, the traditional method is unable to take devices out of the latch-up owing to the small resistance range. To solve this problem, the paper proposes an improved design for the resistor in front of the DC-DC buck converter. The proposed method enables the devices to exit the latch-up by increasing the resistance range according to the input characteristic of the DC-DC buck converter. The paper quantifies the range of the resistor through the parametric model containing the resistor and the DC-DC buck converter. Two CMOS devices are chosen for pulsed laser experiments, verifying that the proposed method increases the resistance ranges by 300% to 400% compared to the conventional method. It is also demonstrated that the proposed method exits the devices from latch-up within the resistor ranges. That is, the resistance ranges of 34 Ω~41 Ω and 51 Ω~56 Ω reduce the latch-up currents of the devices to below holding currents of 72.1 mA and 24.2 mA, respectively.

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Laser SEU sensitivity mapping of deep submicron CMOS SRAM

Yu¹,

Gao²,

Chen³

et al. 2014

J. Semicond.

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The pulsed laser facility for SEU sensitivity mapping is utilized to study the SEU sensitive regions of a 0.18 m CMOS SRAM cell. Combined with the device layout micrograph, SEU sensitivity maps of the SRAM cell are obtained. TCAD simulation work is performed to examine the SEU sensitivity characteristics of the SRAM cell. The laser mapping experiment results are discussed and compared with the electron micrograph information of the SRAM cell and the TCAD simulation results. The results present that the test technique is reliable and of high mapping precision for the deep submicron technology device.

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SEE characteristics of small feature size devices by using laser backside testing

Cited by 3 publications

References 20 publications

Experiment Study of Single Event Functional Interrupt in Analog-to-Digital Converters Using a Pulsed Laser

Experiment Study of Single Event Functional Interrupt in Analog-to-Digital Converters Using a Pulsed Laser

Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Laser SEU sensitivity mapping of deep submicron CMOS SRAM

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