Security challenges during VLSI test

Hély, David; Rosenfeld, Kurt; Karri, Ramesh

doi:10.1109/newcas.2011.5981325

Cited by 10 publications

(3 citation statements)

References 11 publications

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“…The proposed method described hereafter reuses scan chain-based test methods and Logic built in self-test (LBIST) methods. Leveraging these methods speed up the PUF enrollment operation thanks to the known efficiency of scan chain operations and also allows to benefit from the dedicated security add-ons proposed in the literature to secure the IC testing infrastructures [11] and consequently address the security issues related to the enrollment. Connecting the PUF enrollment hardware module to the test infrastructure makes the use of standardized test access mechanism available to perform the enrollment during the post manufacturing operations.…”

Section: B Leveraging Secure Ic Testing Methods For Puf Enrollmentmentioning

confidence: 99%

PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community

Pour

Beroulle

Cambou

et al. 2020

2020 IEEE European Test Symposium (ETS)

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Physically Unclonable Functions (PUFs) allow to extract unique fingerprints from silicon chips. The applications are numerous: chip identification, chip master key extraction, authentication protocol, unique seeding, etc. However, secure usage of PUF requires some precautions. This paper reviews industrial concerns associated with PUF operation, including those occurring before and after market. Namely, starting from PUF "secure" specifications, aligned with state-of-the-art standards, we explore innovative techniques to handle enrollment and subsequent PUF queries, in nominal as well as in adversarial environment.

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Section: B Leveraging Secure Ic Testing Methods For Puf Enrollmentmentioning

confidence: 99%

PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community

Pour

Beroulle

Cambou

et al. 2020

2020 IEEE European Test Symposium (ETS)

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“…Several scan-based attacks on hardware implementations of DES and AES have been demonstrated [Mukhopadhyay et al 2005;Bo et al 2006], showing that test facilities are an ideal starting point for identification of relevant internal nodes and for retrieving confidential information. Several test scan attack countermeasures have been published, but a universal minimum-cost solution for protection against test security threats [Hely et al 2011] does not exist.…”

Section: Secure By Designmentioning

confidence: 99%

Architectures of flexible symmetric key crypto engines—a survey

et al. 2013

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Throughput, flexibility, and security form the design trilogy of reconfigurable crypto engines; they must be carefully considered without reducing the major role of classical design constraints, such as surface, power consumption, dependability, and cost. Applications such as network security, Virtual Private Networks (VPN), Digital Rights Management (DRM), and pay per view have drawn attention to these three constraints. For more than ten years, many studies in the field of cryptographic engineering have focused on the design of optimized high-throughput hardware cryptographic cores (e.g., symmetric and asymmetric key block ciphers, stream ciphers, and hash functions). The flexibility of cryptographic systems plays a very important role in their practical application. Reconfigurable hardware systems can evolve with algorithms, face up to new types of attacks, and guarantee interoperability between countries and institutions. The flexibility of reconfigurable crypto processors and crypto coprocessors has reached new levels with the emergence of dynamically reconfigurable hardware architectures and tools. Last but not least, the security of systems that handle confidential information needs to be thoroughly evaluated at the design stage in order to meet security objectives that depend on the importance of the information to be protected and on the cost of protection. Usually, designers tackle security problems at the same time as other design constraints and in many cases target only one security objective, for example, a side-channel attack countermeasures, fault tolerance capability, or the monitoring of the device environment. Only a few authors have addressed all three design constraints at the same time. In particular, key management security (e.g., secure key generation and transmission, the use of a hierarchical key structure composed of session keys and master keys) has frequently been neglected to the benefit of performance and/or flexibility. Nevertheless, a few authors propose original processor architectures based on multi-crypto-processor structures and reconfigurable cryptographic arrays. In this article, we review published works on symmetric key crypto engines and present current trends and design challenges.

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“…It is difficult, even unattainable, to ensure full fault detection using conventional AC and DC electrical testing techniques. An additional security issue comes from fake circuits designed to avoid identification by conventional testing techniques [2]. To differentiate the counterfeit, forged, or damaged ICs from the authentic ICs, straightforward, thorough, non-destructive, and ubiquitous inspection and testing methods are needed.…”

Section: Introductionmentioning

confidence: 99%