Secure hardware IP of GLRT cascade using color interval graph based embedded fingerprint for ECG detector

Abstract

This paper presents a security aware design methodology to design secure generalized likelihood ratio test (GLRT) hardware intellectual property (IP) core for electrocardiogram (ECG) detector against IP piracy and fraudulent claim of IP ownership threats. Integrating authentic (secure version) GLRT hardware IP core in the system-on-chip (SoC) of ECG detectors is paramount for reliable operation and estimation of ECG parametric data, such as Q wave, R wave and S wave (QRS) complex detection. A pirated GLRT hardware IP integrated into an ECG detector may result in an unreliable/erratic estimation of ECG parametric data that can be hazardous and fatal for the end patient. The proposed methodology presents an integrated design flow to secure micro GLRT and GLRT cascade hardware IP cores for the ECG detector, using the colored interval graph (CIG) framework based fingerprint biometric, during high level synthesis (HLS). The proposed approach integrates a fingerprint biometric based security constraint generation process for securing the GLRT hardware IP core. This paper also presents a secure register transfer level (RTL) datapath design corresponding to micro GLRT and GLRT cascade hardware IP cores with embedded IP vendor's fingerprint. The proposed secure GLRT hardware IP core embedded with fingerprint biometric achieves superior results in terms of probability of coincidence and tamper tolerance than other security approaches. More explicitly, the proposed approach reports a significantly lower value of probability of coincidence and stronger value for tamper tolerance. Further, the proposed approach incurs zero design cost overhead.