SeaStar Interconnect: Balanced Bandwidth for Scalable Performance

Brightwell, Ron; Predretti, K.T.; Underwood, Keith D.; Hudson, Trammell

doi:10.1109/mm.2006.65

Cited by 93 publications

(64 citation statements)

References 5 publications

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“…The objective of this paper is acceleration of MPI by means of hardware supports on the NIC with higher scalability without spoiling minimum latency. NICs such as QsNET-II [1], SeaStar [2] and ALPU [5] are off-loading MPI queue processing on a slow embedded CPU or limited hardwired logic. On the other hand, we try to off-load MPI queue processing more partially than ALPU to a small accelerator on a NIC.…”

Section: Copyright C 2013 the Institute Of Electronics Information Amentioning

confidence: 99%

Network Interface Architecture with Scalable Low-Latency Message Receiving Mechanism

Tanabe

Ohta

2013

IEICE Trans. Inf. & Syst.

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SUMMARYMost of scientists except computer scientists do not want to make efforts for performance tuning with rewriting their MPI applications. In addition, the number of processing elements which can be used by them is increasing year by year. On large-scale parallel systems, the number of accumulated messages on a message buffer tends to increase in some of their applications. Since searching message queue in MPI is time-consuming, system side scalable acceleration is needed for those systems. In this paper, a support function named LHS (Limited-length Head Separation) is proposed. Its performance in searching message buffer and hardware cost are evaluated. LHS accelerates searching message buffer by means of switching location to store limited-length heads of messages. It uses the effects such as increasing hit rate of cache on host with partial offloading to hardware. Searching speed of message buffer when the order of message reception is different from the receiver's expectation is accelerated 14.3 times with LHS on FPGA-based network interface card (NIC) named DIMMnet-2. This absolute performance is 38.5 times higher than that of IBM BlueGene/P although the frequency is 8.5times slower than BlueGene/P. LHS has higher scalability than ALPU in the performance per frequency. Since these results are obtained with partially on loaded linear searching on old Pentium R 4, performance gap will increase using state of art CPU. Therefore, LHS is more suitable for larger parallel systems. The discussions for adopting proposed method to state of art processors and systems are also presented. key words: network interface, MPI, message passing, queue management, low latency communication, scalability

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Section: Copyright C 2013 the Institute Of Electronics Information Amentioning

confidence: 99%

Network Interface Architecture with Scalable Low-Latency Message Receiving Mechanism

Tanabe

Ohta

2013

IEICE Trans. Inf. & Syst.

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“…Brightwell et al [24], [25] and [26] and Pedretti et al [27] analyze many aspects of network performance but do not evaluate power as part of their experiment. We have found no work that measures energy in-situ at any scale as it relates to network tuning.…”

Section: Related Workmentioning

confidence: 99%

Measuring and tuning energy efficiency on large scale high performance computing platforms.

Laros¹

2011

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Recognition of the importance of power in the field of High Performance Computing, whether it be as an obstacle, expense or design consideration, has never been greater and more pervasive. While research has been conducted on many related aspects, there is a stark absence of work focused on large scale High Performance Computing. Part of the reason is the lack of measurement capability currently available on small or large platforms. Typically, research is conducted using coarse methods of measurement such as inserting a power meter between the power source and the platform, or fine grained measurements using custom instrumented boards (with obvious limitations in scale). To collect the measurements necessary to analyze real scientific computing applications at large scale, an in-situ measurement capability must exist on a large scale capability class platform.In response to this challenge, we exploit the unique power measurement capabilities of the Cray XT architecture to gain an understanding of power use and the effects of tuning. We apply these capabilities at the operating system level by deterministically halting cores when idle. At the application level, we gain an understanding of the power requirements of a range of important DOE/NNSA production scientific computing applications running at large scale (thousands of nodes), while simultaneously collecting current and voltage measurements on the hosting nodes. We examine the effects of both CPU and network bandwidth tuning and demonstrate energy savings opportunities of up to 39% with little or no impact on run-time performance. Capturing scale effects in our 3 experimental results was key. Our results provide strong evidence that next generation large-scale platforms should not only approach CPU frequency scaling differently, but could also benefit from the capability to tune other platform components, such as the network, to achieve energy efficient performance. 5Acknowledgments I would like to acknowledge the following people who have contributed in various ways, all of which significant, to the successful completion of this work: Dr.

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“…We do this for the Seastar communication hardware on the Red Storm machine. The Seastar is a high performance network interface that utilizes the AMD HyperTransport Interface and proprietary mesh interconnect for data transfers between Cray XT nodes [5]. At the hardware layer the data transfers take the form of arbitrary physical-addressed DMA operations.…”

Section: Chapter 5 Integrating Palacios and Kittenmentioning

confidence: 99%

“…Each XT4 node on this machine contains a quad-core AMD Budapest processor running at 2.2 GHz with 4 GB of RAM. The nodes are interconnected with a Cray Seastar 2.2 mesh network [5]. Each node can simultaneously send and receive at a rate of 2.1 GB/s via MPI.…”

Section: Testbedmentioning

confidence: 99%

Palacios and Kitten : high performance operating systems for scalable virtualized and native supercomputing.

Widener¹,

Jaconette²,

Bridges³

et al. 2009

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Palacios and Kitten are new open source tools that enable applications, whether ported or not, to achieve scalable high performance on large machines. They provide a thin layer over the hardware to support both full-featured virtualized environments and native code bases. Kitten is an OS under development at Sandia that implements a lightweight kernel architecture to provide predictable behavior and increased flexibility on large machines, while also providing Linux binary compatibility. Palacios is a VMM that is under development at Northwestern University and the University of New Mexico. Palacios, which can be embedded into Kitten and other OSes, supports existing, unmodified applications and operating systems by using virtualization that leverages hardware technologies. We describe the design and implementation of both Kitten and Palacios. Our benchmarks show that they provide near native, scalable performance. Palacios and Kitten provide an incremental path to using supercomputer resources that is not performance-compromised.3 Acknowledgment

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SeaStar Interconnect: Balanced Bandwidth for Scalable Performance

Cited by 93 publications

References 5 publications

Network Interface Architecture with Scalable Low-Latency Message Receiving Mechanism

Network Interface Architecture with Scalable Low-Latency Message Receiving Mechanism

Measuring and tuning energy efficiency on large scale high performance computing platforms.

Palacios and Kitten : high performance operating systems for scalable virtualized and native supercomputing.

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