Seamless Integrated Simulation in Design and Verification Flow for Safety-Critical Systems

Weissnegger, Ralph; Schuß, Markus; Kreiner, Christian; Pistauer, Markus; Römer, Kay Uwe; Steger, Christian

doi:10.1007/978-3-319-45480-1_29

Cited by 5 publications

(1 citation statement)

References 8 publications

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“…The formalization of the FTA and the SFI structure are realized with the UML. Approaches such as [5,20] are also using the UML to support safety assessment. [5] provides a model-to-model transformation to map a UML specification to a executable model based on the Action Language for Foundational UML.…”

Section: Related Workmentioning

confidence: 99%

Verification of Component Fault Trees Using Error Effect Simulations

Reiter¹,

Zeller²,

Hoefig³

et al. 2017

Model-Based Safety and Assessment

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The growing complexity of safety-relevant systems causes an increasing effort for safety assurance. The reduction of development costs and time-to-market, while guaranteeing safe operation, is therefore a major challenge. In order to enable efficient safety assessment of complex architectures, we present an approach, which combines deductive safety analyses, in form of Component Fault Trees (CFTs), with an Error Effect Simulation (EES) for sanity checks. Both CFTs and the EES provide a modular, reusable and compositional safety analysis. The combination reduces the drawbacks of both analyses, such as the subjective failure propagation assumptions in the CFTs or the determination of relevant fault scenarios for the EES. Since both are applicable throughout the whole design process, they support continuous model refinement and the reuse of conducted safety analysis and simulation models. Hence, safety goal violations can be identified in early design stages and the reuse of conducted safety analyses reduces the overhead for safety assessment.

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Section: Related Workmentioning

confidence: 99%

Verification of Component Fault Trees Using Error Effect Simulations

Reiter¹,

Zeller²,

Hoefig³

et al. 2017

Model-Based Safety and Assessment

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show abstract

SHARC - Simulation and Verification of Hierarchical Embedded Microelectronic Systems

Weissnegger

Kreiner

Pistauer

et al. 2017

Procedia Computer Science

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SoC-Level Safety-Oriented Design Process in Electronic System Level Development Environment

Chen

2021

J CIRCUIT SYST COMP

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We propose a safety-oriented design process for IP-based safety-critical system-on-chip (SoC). The proposed safety process can facilitate the measurement of the robustness based on the safety-related metrics and scales of failure-induced risks in a system that can be employed to locate the critical components for protection to effectively diminish the influence of failures on the system. The risk reduction phase is activated to enhance the robustness of critical components identified by vulnerability analysis if the measured robustness is insufficient. An SoC-level safety design platform was built on the SystemC Synopsys Platform Architect MCO to demonstrate the core idea of the safety process. The safety-oriented design process for an ARM-embedded SoC modeled at the TLM level was conducted to demonstrate the feasibility of our safety approach.

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Seamless Integrated Simulation in Design and Verification Flow for Safety-Critical Systems

Cited by 5 publications

References 8 publications

Verification of Component Fault Trees Using Error Effect Simulations

Verification of Component Fault Trees Using Error Effect Simulations

SHARC - Simulation and Verification of Hierarchical Embedded Microelectronic Systems

SoC-Level Safety-Oriented Design Process in Electronic System Level Development Environment

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