SeaMicro SM10000-64 server: Building datacenter servers using cell phone chips

Dhodapkar, Ashutosh S.; Lauterbach, G.; Lie, Sean; Mallick, D.; Bauman, Jim; Kanthadai, Sundar; Kuzuhara, Toru; Shen, Gene; Xu, Min; Zhang, Wenjun

doi:10.1109/hotchips.2011.7477504

Cited by 10 publications

(9 citation statements)

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“…While the actual choice of topology depends on system specifics, low-dimensional k-ary n-cubes (e.g., 3D torii) seem wellmatched to rack-scale deployments [18].…”

Section: Communication Protocolmentioning

confidence: 99%

Scale-out NUMA

Novaković

Daglis

Bugnion

et al. 2014

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

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Emerging datacenter applications operate on vast datasets that are kept in DRAM to minimize latency. The large number of servers needed to accommodate this massive memory footprint requires frequent server-to-server communication in applications such as key-value stores and graph-based applications that rely on large irregular data structures. The fine-grained nature of the accesses is a poor match to commodity networking technologies, including RDMA, which incur delays of 10-1000x over local DRAM operations.We introduce Scale-Out NUMA (soNUMA) -an architecture, programming model, and communication protocol for low-latency, distributed in-memory processing. soNUMA layers an RDMA-inspired programming model directly on top of a NUMA memory fabric via a stateless messaging protocol. To facilitate interactions between the application, OS, and the fabric, soNUMA relies on the remote memory controller -a new architecturally-exposed hardware block integrated into the node's local coherence hierarchy. Our results based on cycle-accurate full-system simulation show that soNUMA performs remote reads at latencies that are within 4x of local DRAM, can fully utilize the available memory bandwidth, and can issue up to 10M remote memory operations per second per core.

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“…While the actual choice of topology depends on system specifics, low-dimensional k-ary n-cubes (e.g., 3D torii) seem wellmatched to rack-scale deployments [18].…”

Section: Communication Protocolmentioning

confidence: 99%

Scale-out NUMA

Novaković

Daglis

Bugnion

et al. 2014

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

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“…Second, system integrators are starting to offer glueless fabrics that can seamlessly interconnect hundreds of server nodes into fat-tree or torus topologies [18]. For instance, Calxeda's on-chip fabric router encapsulates Ethernet frames while energy-efficient processors run the standard TCP/IP and UDP/IP protocols as if they had a standard Ethernet NIC [16].…”

Section: Datacenter Trendsmentioning

confidence: 99%

Scale-out NUMA

et al. 2014

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Emerging datacenter applications operate on vast datasets that are kept in DRAM to minimize latency. The large number of servers needed to accommodate this massive memory footprint requires frequent server-to-server communication in applications such as key-value stores and graph-based applications that rely on large irregular data structures. The fine-grained nature of the accesses is a poor match to commodity networking technologies, including RDMA, which incur delays of 10-1000x over local DRAM operations. We introduce Scale-Out NUMA (soNUMA)-an architecture, programming model, and communication protocol for low-latency, distributed in-memory processing. soNUMA layers an RDMA-inspired programming model directly on top of a NUMA memory fabric via a stateless messaging protocol. To facilitate interactions between the application, OS, and the fabric, soNUMA relies on the remote memory controller-a new architecturally-exposed hardware block integrated into the node's local coherence hierarchy. Our results based on cycle-accurate full-system simulation show that soNUMA performs remote reads at latencies that are within 4x of local DRAM, can fully utilize the available memory bandwidth, and can issue up to 10M remote memory operations per second per core.

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“…Recent high-density chassis-and rack-scale systems are based on server processors with a few cores and an on-chip NI [9,12,26]. Although integrated, the whole NI logic is still placed at the chip's edge, close to the pins that connect the chip to the network.…”

Section: Conventional Edge-based Nimentioning

confidence: 99%

“…Recently, server performance and energy considerations have led to the emergence of highly integrated chassis-and rack-scale systems, such as HP Moonshot [22], Boston Viridis [8], and AMD's SeaMicro [12]. These systems interconnect a large number of servers, each with an on-chip NI, using a supercomputer-like lossless fabric.…”

Section: Application and Technology Trendsmentioning

confidence: 99%

Manycore network interfaces for in-memory rack-scale computing

Daglis¹,

Novaković²,

Bugnion³

et al. 2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

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Datacenter operators rely on low-cost, high-density technologies to maximize throughput for data-intensive services with tight tail latencies. In-memory rack-scale computing is emerging as a promising paradigm in scale-out datacenters capitalizing on commodity SoCs, low-latency and highbandwidth communication fabrics and a remote memory access model to enable aggregation of a rack's memory for critical data-intensive applications such as graph processing or key-value stores. Low latency and high bandwidth not only dictate eliminating communication bottlenecks in the software protocols and off-chip fabrics but also a careful on-chip integration of network interfaces. The latter is a key challenge especially in architectures with RDMA-inspired one-sided operations that aim to achieve low latency and high bandwidth through on-chip Network Interface (NI) support. This paper proposes and evaluates network interface architectures for tiled manycore SoCs for in-memory rack-scale computing. Our results indicate that a careful splitting of NI functionality per chip tile and at the chip's edge along a NOC dimension enables a rack-scale architecture to optimize for both latency and bandwidth. Our best manycore NI architecture achieves latencies within 3% of an idealized hardware NUMA and efficiently uses the full bisection bandwidth of the NOC, without changing the on-chip coherence protocol or the core's microarchitecture.

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SeaMicro SM10000-64 server: Building datacenter servers using cell phone chips

Cited by 10 publications

References 0 publications

Scale-out NUMA

Scale-out NUMA

Scale-out NUMA

Manycore network interfaces for in-memory rack-scale computing

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