SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip

Zhao, Dixian; Yi, Wang

doi:10.1109/tc.2008.86

Cited by 160 publications

(86 citation statements)

References 29 publications

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“…[31,37,40,67,69,[75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94]. Specifically, Table 2 compares the proposed design to [31,37,40,67,79,83] in terms of area, gain, HPBW and bandwidth.…”

Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning

confidence: 99%

“…[78][79][80]. The UWB antenna design approach can provide high bandwidth, low power and short-range communication for WiNoCs.…”

Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning

confidence: 99%

“…However, the UWB-based antenna in Ref. [78][79][80], implemented in a 180 nm CMOS technology as a meander-type dipole antenna with a length of about 3 mm, and integrated in a complete on-chip transceiver, allows for a transmission range limited to 1 mm. The area occupation of the antenna in the layout of Ref.…”

Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning

confidence: 99%

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Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

Gutiérrez¹

2017

JLPEA

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Abstract:To allow fast communication-at several Gb/s-of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and can be implemented on-chip using the top metal layer of a conventional silicon CMOS (Complementary Metal Oxide Semiconductor) technology. The antenna performance is discussed in the paper and is compared to the state-of-the-art, including the zig-zag antenna topology that is typically used in literature as a reference for WiNoC. The proposed bow-tie antenna design for WiNoC stands out for its good trade-off among bandwidth, gain, size and beamwidth vs. the state-of-the-art.

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Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning

confidence: 99%

“…[78][79][80]. The UWB antenna design approach can provide high bandwidth, low power and short-range communication for WiNoCs.…”

Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning

confidence: 99%

Section: Comparison Of the Designed Antenna Vs The State-of-the-artmentioning

confidence: 99%

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Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

Gutiérrez¹

2017

JLPEA

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“…gies for both 2D and 3D integrated circuits [45]. Finally, heterogeneous networks on chip are devised to serve the different characteristics of these structures in the hybrid memory hierarchy.…”

Section: Runtime-aware Architecturesmentioning

confidence: 99%

“…Since these traditional approaches for NoC's do not scale for many-cores, it is required to explore novel and scalable NoC approaches such as wireless interconnects, which can be used in conjunction with traditional wired and optical interconnects in novel RAA NoC topolo- gies for both 2D and 3D integrated circuits [45]. Finally, heterogeneous networks on chip are devised to serve the different characteristics of these structures in the hybrid memory hierarchy.…”

mentioning

confidence: 99%

Runtime-Aware Architectures: A First Approach

Valero

Moretó

Casas

et al. 2014

JSFI

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In the last few years, the traditional ways to keep the increase of hardware performance at the rate predicted by Moore's Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software stack thanks to a well defined Instruction Set Architecture (ISA). This simple interface allowed developing applications without worrying too much about the underlying hardware, while hardware designers were able to aggressively exploit instruction-level parallelism (ILP) in superscalar processors. With the irruption of multi-cores and parallel applications, this simple interface started to leak. As a consequence, the role of decoupling again applications from the hardware was moved to the runtime system. Efficiently using the underlying hardware from this runtime without exposing its complexities to the application has been the target of very active and prolific research in the last years.Current multi-cores are designed as simple symmetric multiprocessors (SMP) on a chip. However, we believe that this is not enough to overcome all the problems that multi-cores already have to face. It is our position that the runtime has to drive the design of future multi-cores to overcome the restrictions in terms of power, memory, programmability and resilience that multi-cores have. In this paper, we introduce a first approach towards a Runtime-Aware Architecture (RAA), a massively parallel architecture designed from the runtime's perspective.Keywords: Parallel architectures, runtime system, hardware-software co-design. IntroductionWhen uniprocessors were the norm, Instruction Level Parallelism (ILP) and Data Level Parallelism (DLP) were widely exploited to increase the number of instructions executed per cycle. The main hardware designs that were used to exploit ILP were superscalar and Very Long Instruction Word (VLIW) processors. The VLIW approach requires to statically determine dependencies between instructions and schedule them. However, since it is not possible in general to obtain optimal schedulings at compile time, VLIW does not fully exploit the potential ILP that many workloads have. Superscalar designs try to overcome the increasing memory latencies, the so called Memory Wall [42], by using Out of Order (OoO) and speculative executions [18]. Additionally, techniques such as prefetching, to start fetching data from the memory ahead of time, deep memory hierarchies, to exploit the locality that many programs have, and large reorder buffers, to increase the number of speculative instructions exposed to the hardware, have been also used to enhance superscalar processors performance. DLP is typically expressed explicitly at the software layer and it consisted in a parallel operation on multiple data performed by multiple independent instructions, or by multiple independent threads. In uniprocessors, the Instruction Set Architecture (ISA) was in charge of decoupling the application, written in a highlevel programming language, and the hardware, as we can see in the left hand side of Figure 1. In this ...

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Metasurface‐Programmable Wireless Network‐On‐Chip

2022

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This paper introduces the concept of smart radio environments, currently intensely studied for wireless communication in metasurface‐programmable meter‐scaled environments (e.g., inside rooms), on the chip scale. Wireless networks‐on‐chips (WNoCs) are a candidate technology to improve inter‐core communication on chips but current proposals are plagued by a dilemma: either the received signal is weak, or it is significantly reverberated such that the on–off‐keying modulation speed must be throttled. Here, this vexing problem is overcome by endowing the wireless on‐chip environment with in situ programmability which enables the shaping of the channel impulse response (CIR); thereby, a pulse‐like CIR shape can be imposed despite strong multipath propagation and without entailing a reduced received signal strength. First, a programmable metasurface suitable for integration in the on‐chip environment (“on‐chip reconfigurable intelligent surface”) is designed and characterized. Second, its configuration is optimized to equalize selected wireless on‐chip channels “over the air.” Third, by conducting a rigorous communication analysis, the feasibility of significantly higher modulation speeds with shaped CIRs is evidenced. The results introduce a programmability paradigm to WNoCs which boosts their competitiveness as complementary on‐chip interconnect solution.

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SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip

Cited by 160 publications

References 29 publications

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

Runtime-Aware Architectures: A First Approach

Metasurface‐Programmable Wireless Network‐On‐Chip

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