Scratchpad memory management for portable systems with a memory management unit

Abstract

In this paper, we present a dynamic scratchpad memory allocation strategy targeting a horizontally partitioned memory subsystem for contemporary embedded processors. The memory subsystem is equipped with a memory management unit (MMU), and physically addressed scratchpad memory (SPM) is mapped into the virtual address space. A small minicache is added to further reduce energy consumption and improve performance. Using the MMU's page fault exception mechanism, we track page accesses and copy frequently executed code sections into the SPM before they are executed. Because the minimal transfer unit between the external memory and the SPM is a single memory page, good code placement is of great importance for the success of our method. Based on profiling information, our postpass optimizer divides the application binary into pageable, cacheable, and uncacheable regions. The latter two are placed at fixed locations in the external memory, and only pageable code is copied on demand to the SPM from the external memory. Pageable code is grouped into sections whose sizes are equal to the physical page size of the MMU. We discuss code grouping techniques and also analyze the effect of the minicache on execution time and energy consumption. We evaluate our SPM allocation strategy with twelve embedded applications, including MPEG-4. Compared to a fully-cached configuration, on average we achieve a 12% improvement in runtime performance and a 33% reduction in energy consumption by the memory system.

Core Working Set Based Scratchpad Memory Management

“…However, the proposed method differs from Egger's method not by utilizing the profiling information, but by monitoring the runtime access pattern. For a fair comparison, we adopt a hybrid on-chip memory configuration of 16 KB data SPM plus 4 KB data mini-cache [21] in this experiment. The SPM is managed by the proposed method and Egger's method, respectively.…”

“…There are two possible causes of the disparity. First, the method in [21] adopts some empirical factors, such as the cache miss ratio and the average page miss number. The accuracy of these parameters is closely related to the application's characteristics and the profiling numbers.…”

A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems

“…Egger et al [22] used a compile-time technique to manage the MMU, and loads tasks' code into the SPM dynamically. In this work, the compiled binary has to be processed by the post-optimizer, a tool they developed, in order to make the final binary optimized for their memory architecture.…”

“…The page table entries are modified accordingly. This mechanism is somewhat similar to the one used in [22], but this work is still interesting as it does not need postcompile processing or specialized hardware in addition to the MMU. It is also transparent to the application programmers and there is no API needed.…”

“…It is also transparent to the application programmers and there is no API needed. Like in [22], this work is only based on simulation, not a real platform. Furthermore, there is no DMA component to load/unload the SPM, which results in reduced performance.…”