VLSI implementation of image compressor using probabilistic run length coding

Abstract

Multimedia applications, such as image processing including image and video transfer, heavily rely on reduction. The traditional device methods to picture reduction use more space, energy, and processing time. The majority of current efforts use the Golomb‐Rice encoding, due to its larger memory requirement and higher computing difficulty. So, this research concentrated on hardware design‐oriented probability run length (PRL) coding technique based on lossless colour image compression. The block truncation coding (BTC) features of the compression process are used by the suggested PRL method. The proposed image compression hardware consists of various modules such as a Parameter calculator, fuzzy table, bitmap generator, BTC parameters training, prediction, and error control, and PRL‐based finite state machine (PRL‐FSM). The proposed image compressor utilizes the parameter calculator block, which estimates the block type based on the image pixel intensities for each sub‐block. Thus, each block of the image is compressed by using a new block type and generates a variable block size. The proposed method utilizes the PRL‐BTC encoding method, which also calculates the probability of error between the compressed image to the test image. The process is iterated until the performance trade‐off between hardware cost and compression ratio (CR) is achieved. Hence, both smooth regions and non‐smooth regions of images are perfectly compressed by the probability‐based block selection. The simulation results show that the proposed method resulted in a better area, power, delay metrics, peak signal‐to‐noise ratio (PSNR), and CR compared to the state of art approaches.