Scheduling with bus access optimization for distributed embedded systems

Eles, Petru; Doboli, Alex; Pop, Paul; Peng, Zebo

doi:10.1109/92.894152

Cited by 105 publications

(86 citation statements)

References 58 publications

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“…We represent an embedded program module M as a directed dependency graph G = {V, E S , E C }, where V is a set of nodes and E S and E C are sets of simple and conditional edges, respectively. The main difference from the model in [7] is that we will permit loops in the graph, i.e., the dependency graph G does not have to be acyclic, and we will consider program instructions instead of processes. Moreover, it is not required that the graph has to be polar, i.e., several source and sink nodes are possible.…”

Section: Application Modelmentioning

confidence: 99%

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Optimization of Assertion Placement in Time-Constrained Embedded Systems

Izosimov

Peng

Lora

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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Abstract-We present an approach for optimization of assertion placement in time-constrained HW/SW modules for detection of errors due to transient and intermittent faults. During the design phases, these assertions have to be inserted into the executable code and, hence, will always be executed with the corresponding code branches. As the result, they can significantly increase execution time of a module, in particular, contributing to a much longer execution of the worst case, and cause deadline misses. Assertions have different characteristics such as tightness (or "local error coverage") and execution latency. Taking into account these properties can increase efficiency of assertion checks in time-constrained embedded HW/SW modules. We have developed a design optimization framework, which (1) identifies candidate locations for assertions, (2) associates a candidate assertion to each location, and (3) selects a set of assertions in terms of performance degradation and assertion tightness. Experimental results have shown the efficiency of the proposed techniques.

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Section: Application Modelmentioning

confidence: 99%

“…To represent application behavior, we have adapted the conditional process graph model proposed in [7] for the program instruction level. We represent an embedded program module M as a directed dependency graph G = {V, E S , E C }, where V is a set of nodes and E S and E C are sets of simple and conditional edges, respectively.…”

Section: Application Modelmentioning

confidence: 99%

Optimization of Assertion Placement in Time-Constrained Embedded Systems

Izosimov

Peng

Lora

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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show abstract

“…Even in the case of such low bus utilization, no strong guarantees regarding QoS can be provided. Authors in [15], [16], [17] presented several bus access optimizations for enhancing predictability in MPSoCs, but none of them has been demonstrated and validated on a real platform target, hence their modeling abstractions have not been fully validated.…”

Section: Related Workmentioning

confidence: 99%

Adaptive TDMA bus allocation and elastic scheduling: A unified approach for enhancing robustness in multi-core RT systems

Burgio

Ruggiero

Esposito

et al. 2010

2010 IEEE International Conference on Computer Design

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Abstract-Next-generation real-time systems will be increasingly based on heterogeneous MPSoC design paradigms, where predictability and performance will be key issues to deal with. Such issues can be tackled both at the hardware level, by embedding technologies such as TDMA busses, and at the OS level, where suitable scheduling techniques can improve performance and reduce energy consumption. Among these, elastic scheduling has been proved to provide satisfactory results by dynamically reducing task periods at run-time to ensure the highest utilization possible of the processors. On the other hand, elastic scheduling lowers the degree of predictability and increases the complexity of the analysis at the system level. This reduces the benefits given by the TDMA bus, which relies on the high level task analysis for a robust and efficient slot allocation. Starting from this consideration, we propose a system where the elastic scheduling and the TDMA bus work synergistically. We introduce a QoS-aware adaptive bus service which takes the best of both techniques, mitigating their drawbacks at the same time. We show how the overhead introduced by coordination action is small, and it is however dominated by the benefits of the overall strategy in terms of performance and predictability guarantees.

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“…A process or a message in the application is placed in the ReadyList if all its predecessors have already been scheduled. The list is ordered based on the priorities presented in [73]. The algorithm terminates when all processes and messages have been visited.…”

Section: Multi-cluster Analysis and Schedulingmentioning

confidence: 99%