Scheduling of multiple network packet processing applications using Pythia

Giakoumakis, Giannis; Papadogiannaki, Eva; Vasiliadis, Giorgos; Ioannidis, Sotiris

doi:10.1016/j.comnet.2022.109006

Cited by 3 publications

(1 citation statement)

References 24 publications

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“…Furthermore, Papadogiannaki et al [30] proposed a scheduling approach that, based on performance policies (such as high throughput or low power consumption), determines the most suitable combination of heterogeneous devices (i.e., CPU, integrated, or discrete GPUs) for efficient execution of network packet processing workloads (such as DPI or packet encryption). Similarly, in Pythia [31,32], authors add the support for concurrent execution of different network packet processing applications across multiple and heterogeneous devices. In APUNet [33], authors propose the utilization of integrated GPUs to accelerate packet processing workloads without paying the overheads of memory transactions between the host and discrete GPUs.…”

Section: Gpu-based Pattern Matchingmentioning

confidence: 99%

The Diversification and Enhancement of an IDS Scheme for the Cybersecurity Needs of Modern Supply Chains

Deyannis

Papadogiannaki

Chrysos³

et al. 2022

Electronics

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Despite the tremendous socioeconomic importance of supply chains (SCs), security officers and operators are faced with no easy and integrated way for protecting their critical, and interconnected, infrastructures from cyber-attacks. As a result, solutions and methodologies that support the detection of malicious activity on SCs are constantly researched into and proposed. Hence, this work presents the implementation of a low-cost reconfigurable intrusion detection system (IDS), on the edge, that can be easily integrated into SC networks, thereby elevating the featured levels of security. Specifically, the proposed system offers real-time cybersecurity intrusion detection over high-speed networks and services by offloading elements of the security check workloads on dedicated reconfigurable hardware. Our solution uses a novel framework that implements the Aho–Corasick algorithm on the reconfigurable fabric of a multi-processor system-on-chip (MPSoC), which supports parallel matching for multiple network packet patterns. The initial performance evaluation of this proof-of-concept shows that it holds the potential to outperform existing software-based solutions while unburdening SC nodes from demanding cybersecurity check workloads. The proposed system performance and its efficiency were evaluated using a real-life environment in the context of European Union’s Horizon 2020 research and innovation program, i.e., CYRENE.

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Section: Gpu-based Pattern Matchingmentioning

confidence: 99%