Scheduling divisible loads on partially reconfigurable hardware

Vikram, Karimella; Vasudevan, V.

doi:10.1109/fccm.2006.63

Cited by 1 publication

(3 citation statements)

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“…The result transfer time must then be taken into consideration along with a bus bandwidth constraint. The details of this analysis are given in [26] and [27]. Fig.…”

Section: Discussionmentioning

confidence: 99%

“…Using , we can relate the load fractions and as (24) Using the normalization (2) for PUs and substituting for from (22) and (23) and using (24), can be written as (25) Using (24) and (25), the expression for is (26) The optimum processing time is given by (27) where is given by (26). The value of in (26) can be obtained as follows.…”

Section: A Without Front-endmentioning

confidence: 99%

“…Once has been determined, we can compute the load fractions using (22), (23), (25), and (26). The optimum processing time can then be computed using (27). It may be noted that the intervals of , implied by (34) for different values of , abut each other and, therefore, span a contiguous range of possible values of .…”

Section: A Without Front-endmentioning

confidence: 99%

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Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures

Vikram¹,

Vasudevan

2006

IEEE Trans. VLSI Syst.

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Reconfigurable hybrid processor systems provide a flexible platform for mapping data-parallel applications, while providing considerable speedup over software implementations. However, the overhead for reconfiguration presents a significant deterrent in mapping applications onto reconfigurable hardware. Partial runtime reconfiguration is one approach to reduce the reconfiguration overhead. In this paper, we present a methodology to map data-parallel tasks onto hardware that supports partial reconfiguration. The aim is to obtain the maximum possible speedup, for a given reconfiguration time, bus speed, and computation speed. The proposed approach involves using multiple, identical but independent processing units in the reconfigurable hardware. Under nonzero reconfiguration overhead, we show that there exists an upper limit on the number of processing units that can be employed beyond which further reduction in execution time is not possible. We obtain solutions for the minimum processing time, the corresponding load distribution, and schedule for data transfer. To demonstrate the applicability of the analysis, we present the following: 1) various plots showing the variation of processing time with different parameters; 2) hardware simulations for two examples, viz., 1-D discrete wavelet transform and finite impulse response filter, targeted to Xilinx field-programmable gate arrays (FPGAs); and 3) experimental results for a hardware prototype implemented on a FPGA board.

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“…The result transfer time must then be taken into consideration along with a bus bandwidth constraint. The details of this analysis are given in [26] and [27]. Fig.…”

Section: Discussionmentioning

confidence: 99%