Schedulers as model-based design elements in programmable heterogeneous multiprocessors

Paul, JoAnn M.; Bobrek, Alex; Nelson, Jeffrey E.; Pieper, Joshua J.; Thomas, Donald E.

doi:10.1145/775832.775938

Cited by 17 publications

(13 citation statements)

References 7 publications

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“…This hypothesis was experimentally verified in Ref. 13, which introduced Model-based Scheduling as a design strategy. Here a scheduler on each processing element in a SCHM is designed to the context of both a model of the performance capabilities of other elements in the system and the state of the system.…”

Section: Motivationmentioning

confidence: 83%

“…Motivated by this question, our own prior experimental results, (13) , and some recent SCHM architectures, discussed in the next section, we examined this question in more detail.…”

Section: Best Casementioning

confidence: 99%

“…13 because it motivated a more detailed consideration of the design principles that lead to this paper, as well as provides some insight as to the impact of global scheduling. The system is a simple "multimedia" system consisting of two heterogeneous processors (a Renesas M32R, hereafter referred to as a DSP, and an ARM) to handle a mixture of image and text compression applications.…”

Section: Impacts Of Global Schedulingmentioning

confidence: 99%

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Amdahl’s Law Revisited for Single Chip Systems

Paul

Meyer

2007

Int J Parallel Prog

Self Cite

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Amdahl's Law is based upon two assumptions -that of boundlessness and homogeneity -and so it can fail when applied to single chip heterogeneous multiprocessor designs, and even microarchitecture. We show that a performance increase in one part of the system can negatively impact the overall performance of the system, in direct contradiction to the way Amdahl's Law is instructed. Fundamental assumptions that are consistent with Amdahl's Law are a heavily ingrained part of our computing design culture, for research as well as design. This paper points in a new direction. We motivate that emphasis should be made on holistic, system level views instead of divide and conquer approaches. This, in turn, has relevance to the potential impacts of custom processors, system-level scheduling strategies and the way systems are partitioned. We realize that Amdahl's Law is one of the few, fundamental laws of computing. However, its very power is in its simplicity, and if that simplicity is carried over to future systems, we believe that it will impede the potential of future computing systems.

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Section: Motivationmentioning

confidence: 83%

“…Motivated by this question, our own prior experimental results, (13) , and some recent SCHM architectures, discussed in the next section, we examined this question in more detail.…”

Section: Best Casementioning

confidence: 99%

Section: Impacts Of Global Schedulingmentioning

confidence: 99%

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Amdahl’s Law Revisited for Single Chip Systems

Paul

Meyer

2007

Int J Parallel Prog

Self Cite

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“…A few researches address scheduler architecture and scheduler implementation [5,12,18,21]. In [21], they introduce layered scheduler architecture for programmable heterogeneous multiprocessor system.…”

Section: Related Workmentioning

confidence: 99%

“…In [21], they introduce layered scheduler architecture for programmable heterogeneous multiprocessor system. They focus on defining the hierarchical thread scheduler architecture but not on implementation or optimization of scheduler's performance and area.…”

Section: Related Workmentioning

confidence: 99%

Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip

Cho¹,

Zergainoh²,

Yoo³

et al. 2007

Des Autom Embed Syst

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In multiprocessor system-on-chip, tasks and communications should be scheduled carefully since their execution order affects the performance of the entire system. When we implement an MPSoC according to the scheduling result, we may find that the scheduling result is not correct or timing constraints are not met unless it takes into account the delays of MPSoC architecture. The unexpected scheduling results are mainly caused from inaccurate communication delays and or runtime scheduler's overhead. Due to the big complexity of scheduling problem, most previous work neglects the inter-processor communication, or just assumes a fixed delay proportional to the communication volume, without taking into consideration subtle effects like the communication congestion and synchronization delay, which may change dynamically throughout tasks execution. In this paper, we propose an accurate scheduling model of hardware/software communication architecture to improve timing accuracy by taking into account the effects of dynamic software synchronization and detailed hardware resource constraints such as communication congestion and buffer sharing. We also propose a method for runtime scheduler implementation and consider its performance overhead in scheduling. In particular, we introduce efficient hardware and software scheduler architectures. Furthermore, we address the issue of centralized implementation versus distributed implementation of the schedulers. We investigate the pros and cons of the two different scheduler implementations. Through experiments with significant demonstration examples, we show the effectiveness of the proposed approac

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Power-Performance Modeling and Design for Heterogeneous Multiprocessors

Paul¹,

Meyer²

2007

Designing Embedded Processors

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Schedulers as model-based design elements in programmable heterogeneous multiprocessors

Cited by 17 publications

References 7 publications

Amdahl’s Law Revisited for Single Chip Systems

Amdahl’s Law Revisited for Single Chip Systems

Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip

Power-Performance Modeling and Design for Heterogeneous Multiprocessors

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