Scheduled dataflow: execution paradigm, architecture, and performance evaluation

Abstract

AbstractÐIn this paper, the Scheduled Dataflow (SDF) architectureÐa decoupled memory/execution, multithreaded architecture using nonblocking threadsÐis presented in detail and evaluated against Superscalar architecture. Recent focus in the field of new processor architectures is mainly on VLIW (e.g., IA-64), superscalar, and superspeculative designs. This trend allows for better performance, but at the expense of increased hardware complexity and, possibly, higher power expenditures resulting from dynamic instruction scheduling. Our research deviates from this trend by exploring a simpler, yet powerful execution paradigm that is based on dataflow and multithreading. A program is partitioned into nonblocking execution threads. In addition, all memory accesses are decoupled from the thread's execution. Data is preloaded into the thread's context (registers) and all results are poststored after the completion of the thread's execution. While multithreading and decoupling are possible with control-flow architectures, SDF makes it easier to coordinate the memory accesses and execution of a thread, as well as eliminate unnecessary dependencies among instructions. We have compared the execution cycles required for programs on SDF with the execution cycles required by programs on SimpleScalar (a superscalar simulator) by considering the essential aspects of these architectures in order to have a fair comparison. The results show that SDF architecture can outperform the superscalar. SDF performance scales better with the number of functional units and allows for a good exploitation of Thread Level Parallelism (TLP) and available chip area.

Couillard: Parallel programming via coarse-grained Data-flow Compilation

“…Data-flow is an long standing idea in the parallel computing community, with a vast amount of work on both pure and hybrid architectures [23,13,7]. Dataflow techniques are widely used in areas such as internal computer design and stream processing.…”

Exploiting dataflow to extract Java instruction level parallelism on a tag-based multi-issue semi in-order (TMSI) processor

“…Although dataflow has been studied for more than two decades, actual implementations of the model have failed to deliver the promised performance. Most modern processors utilize complex hardware techniques to detect data and control hazards and dynamic parallelism in order to bring the execution engine closer to an idealized dataflow engine [21]. In this paper, we propose the architecture of Java ILP processor, in which dataflow is exploited to identify stack dependence, reduce redundant stack operations and extract ILP in Java programs.…”

“…Hence the availability of operands of the ready instructions did not immediately "trigger" them to be executed. This execution paradigm is similar to the scheduled dataflow [21]. With instruction scheduler, instructions are easy to be synchronized and managed.…”

“…With instruction scheduler, instructions are easy to be synchronized and managed. Designed in this way, the complexity of instruction issue logic [21] is reduced, out-of-order execution can be implemented and fine-grained parallelism is achieved as in dataflow without a need of the dataflow programming paradigm.…”

Stochastic non-preemptive co-flow scheduling with time-indexed relaxation

“…For instance, processing times can be regarded as independent random variables drawn from given probability distributions. Further, many scenarios do not allow for stopping a transfer once started [9] and thus non-preemptive scheduling strategies are important. The key reasons for practicality of non-preemption The authors are with Purdue University, West Lafayette IN 47907 (email: {mao95, vaneet, chiang}@purdue.edu).…”