Scan Latch Design for Test Applications

Decoder-based Decompression for test sets containing don’t cares

“…It should be mentioned that the latch shown in Fig. 4(b) compares favorably to the latches used in practice, achieving 33% saving in chip area [12]. An estimation of the hardware overhead of the two structures in Fig.…”

“…6. (a) (b) Fig. 4: (a) Clocked D-latch (b) latch design proposed by [12] for scan applications Fig. 6(a) the normal operation of the latch is shown.…”

Output response compaction in RAS-based schemes

“…In 2004, Arslan and Orailoglu [17] presented a scheme based on RAS, although they utilized a different name. In the same year, Sheth and Savir proposed [18] a design for a scan latch that was utilized in [19] to design a latch-based RAS architecture with low hardware overhead. In 2005, Mudlapur, Agrawal and Singh, proposed in [20] a random access scan flip flop, which they subsequently utilized to propose, in [21], a Random Access Scan architecture with reduced overhead.…”