Scan-chain intra-cell defects grading

Abstract

International audienceWith the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. Several works analyze the impact of intra-cell defects w.r.t. the test quality. However, to the best of our knowledge, none of them target intra-cell defects affecting scan flip-flops. This paper presents an evaluation of the effectiveness of the ATPG test patterns in terms of intra-cell defect coverage affecting scan flip-flops. The experimental results show that a meaningful test solution has to be developed to improve the overall defect coverage for the scan chain testing

Scan-Chain Intra-Cell Aware Testing

“…As expected (and already mentioned and explained in a previous work [10]), we obtained a large gap between fault and defect coverage. In fact, the gap can reach up to 43% for the b09 circuit if we consider LOC patterns and 40% for b02 if we consider LOS patterns.…”

“…This evaluation is carried out on 10 industrial multi-million gate designs and the defect coverage gain was estimated for the complete design and for each standard cell type as well. In our previous work [10], we presented a preliminary analysis of intra-cell defects affecting the scan chain. In this paper, we first show that the percentage of intra-cell defects escaping the standard tests is indeed very high (up-to 60%).…”