Scan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems

Experimental Verification of Scan-Architecture-Based Evaluation Technique of SET and SEU Soft-Error Rates at Each Flip-Flop in Logic VLSI Systems

“…This is 0018-9499/$26.00 © 2009 IEEE demonstrated by building ITC'99 benchmark circuits with the proposed or conventional 2-DFF scans and comparing the resultant hardware resources [16]. Delay and power penalties for our scan FF are also reasonable [9], [10]. Because the 2-DFF type scans are usually compatible with the single types, the proposed FF could be implemented in VLSI systems fabricated in the 1-DFF type scan FFs in principle.…”

“…This data transfer operation is controlled by the signals "RadTest", "SE", and "Update". See [9], [10] for its details.…”

“…The system portion works as a conventional sequential element, while the scan portion is used to debug the chip and measure SERs. See [9], [10] for the detail.…”

“…In the previous papers [9], [10], we explained its operation principle, showing logic simulation results. In this paper, we report irradiation test results, experimentally demonstrating the validity of our idea.…”

“…Fig. 1 shows the proposed scan FF [9], [10]. It is based on a 2-DFF type scan FF, which is one of general types of scan circuitry and is widely used in VLSI systems [12] as well as 1-DFF type scan FFs [13]- [15].…”