SCAM: Secured content addressable memory based on homomorphic encryption

Bian, Song; Hiromoto, Masayuki; Satō, Takashi

doi:10.23919/date.2017.7927134

Cited by 8 publications

(12 citation statements)

References 15 publications

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“…Reference [9] proposes a modification to the homomorphic XOR and AND operations, as defined in the FHEW scheme [7], such that searches on a secure CAM do not require expensive operations, such as multiplications, in order to guarantee the integrity of the data at decryption, that is, word matching can be entirely performed through additions, resulting in faster word matching compared to a conventional implementation [30]. Specifically, the word matching function of a CAM employs a XOR-OR variant instead of the original XNOR-AND form, which can be costly to implement in the hardware.…”

Section: Related Work: Cim and Hementioning

confidence: 99%

“…While x i ∈ {0, 1} represents a database entry, y i ∈ {0, 1} refers to a query. The index i represents the individual bits of each word, whose lengths are specified by w. The ciphertext for 1-bit plaintext is denoted as c x and c y and can be as long as (n + 1) log q bits (with n = 1052 and log q = 42, for a medium security standard that uses a 80-bit key, as defined in [9]). (Therefore, a 32-bit data word may translate to a homomorphically encrypted data vector that is >50 000 bits!…”

Section: Related Work: Cim and Hementioning

confidence: 99%

“…In addition to requiring costly operations, such as multiplications and divisions, HE schemes require extremely large datawords due to the sizes of ciphertexts (e.g., in [9], the encryption of a 32-bit word in plain text results in 1 415 232 bits of ciphertext). In this context, dense memories may be useful toward scaling HE applications.…”

Section: Introductionmentioning

confidence: 99%

“…In this article, we propose the use of a novel in-memory (carry select) adder and accumulators that enable energy-efficient searches on homomorphically encrypted data. We leverage the fully additive algorithm proposed in [9] to implement word matching on a secure CAM (SCAM). Our CiM-SCAM engine consists of memory arrays, write buffers, as well as customized sense amplifiers that can perform Boolean operations and additions in memory.…”

Section: Introductionmentioning

confidence: 99%

“…We compare the performance of CiM-SCAM to an application-specific integrated circuit (ASIC) proposed in [9]. The designs considered (SRAM, 1-FeFET, 2T + 1 FeFET, and the ASIC) are implemented with a CMOS 65nm technology node.…”

Section: Introductionmentioning

confidence: 99%

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A Computing-in-Memory Engine for Searching on Homomorphically Encrypted Data

Reis

Niemier

2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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The high volumes of data stored in the cloud, coupled with growing concerns about security and privacy, have motivated research on homomorphic encryption (HE), i.e., a technique that enables computation directly on encrypted data, obviating the need for prior decryption. Recent algorithmic advances have enabled a diverse set of homomorphic operations (e.g., addition, multiplication, and division). Looking at the applications, recent work also suggests extensibility secure, homomorphically encrypted content-addressable memories [or secure content-addressable memories (SCAMs)]. Still, the large datawords that result from homomorphic data encodings (i.e., that must be stored/transferred for computation), compounded with the implicit computational complexity of HE, still impede the deployment of homomorphic computer hardware. As an alternative, computing-in-memory (CiM) architectures could significantly reduce the volume of data transfers for SCAM (and other) applications, leading to considerable energy savings and latency reduction. In this regard, we propose a CiM-compatible engine for SCAM (CiM-SCAM) and analyze the pros and cons of three different memory cells: a 6T CMOS SRAM and two memory cells based on ferroelectric field-effect transistors (FeFETs) (specifically 2T + 1FeFET and 1-FeFET designs). CiM-SCAM leverages in-place copy buffers (IPCBs), along with customized sense amplifiers that include two types of in-memory adders. Our results suggest that energy (and search time) improvements of up to 16× (3.2×) for 1-FeFET memory cells are possible, compared with an application-specific integrated circuit (ASIC) approach. Similar improvements are also possible with SRAM and 2T + 1-FeFET memory cells. For the latter, we achieve up to 13× (3.1×) of energy (speedup). INDEX TERMS Computing-in-memory (CiM), emerging technologies, ferroelectric field-effect transistors (FeFETs), homomorphic encryption (HE), secure content-addressable memory (CAM), SRAMs.

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Section: Related Work: Cim and Hementioning

confidence: 99%

Section: Related Work: Cim and Hementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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