Scaling Up Modulo Scheduling for High-Level Synthesis

Abstract

High-Level Synthesis tools have been increasingly used within the hardware design community to bridge the gap between productivity and the need to design large and complex systems. When targeting heterogeneous systems, where the CPU and the FPGA fabric are both available to perform computations, a design space exploration is usually carried out for deciding which parts of the initial code should be mapped to the FPGA fabric such as the overall system's performance is enhanced by accelerating its computation via dedicated processors. As the targeted systems become more complex and larger, leading to a large design space exploration, the fast estimative of the possible acceleration that can be obtained by mapping certain functionality into the FPGA fabric is of paramount importance. Loop pipelining, which is responsible for the majority of HLS compilation time, is a key optimization towards achieving high-performance acceleration kernels. A new modulo scheduling algorithm is proposed, which reformulates the classical modulo scheduling problem and leads to a reduced number of integer linear problems solved, resulting in large computational savings. Moreover, the proposed approach has a controlled trade-off between solution quality and computation time. Results show the scalability is improved efficiently from quadratic, for the state-of-the-art method, to linear, for the proposed approach, while the optimized loop suffers a 1% (geomean) increment in the total number of cycles.

Non-iterative SDC modulo scheduling for high-level synthesis

“…The GAS modifies Formulation 2 to explicitly separate the problem into its scheduling and allocation parts [9]. GAS considers valid MRTs as individuals for evolution, and uses the SDC Formulation 3 to calculate a schedule for such individuals.…”

“…However, [9] shows that some MRT configurations can make Formulation 3 infeasible. A "feasible" MRT is defined To handle infeasible MRTs, [9] proposes a GA evolution that aims to find feasible MRTs while optimizing the schedule latency concurrently. During evolution, GAS solves (𝑛) SDC problems, where 𝑛 is the loop size.…”

“…Recent works propose to divide the loop pipelining problem in two parts, leaving the allocation part of the problem to be solved by a Genetic Algorithm (GA), while the scheduling part is solved as a standard optimisation problem [9], speeding up the process when compared against the heuristic approaches.…”

“…As in [9], we consider the modulo scheduling problem to be separated into two parts. The scheduling part consists in finding the starting time 𝑡 𝑖 for all instructions 𝐼 𝑖 ∈ 𝑉 such that no dependencies are violated.…”

A CAD-based methodology to optimize HLS code via the roofline model

“…where is the initiation interval of the loop. In order to speedup the result generation, we approximate the as the minimum initiation interval [7] without running time-consuming modulo scheduling algorithms [7,10,14]. Finally, the latency of a single basic block is computed with an adapted ALAP version of the Resource-Constrained List Scheduling algorithm, which includes instruction chaining.…”