Scaling Up Loop Pipelining for High-Level Synthesis: A Non-iterative Approach

Non-iterative SDC modulo scheduling for high-level synthesis

“…The missing points in Figures 5 and 6 show that SDCS fails to produce solutions for larger problems on benchmarks fat, cp, and ac. The results show that GAS and NIS are able to explore solutions more efficiently, indicating the potential of the explicitly MRT exploration approach using Formulation 3 presented in [9,10].…”

“…The results and analysis presented in this section are the first, to the best of our knowledge, to provide valuable insights between the nFUs definition, the modulo schedulers, and the final hardware quality, complementing and providing explanations for the results observed in [10].…”

“…Formulation 2 presents a summarized version of the Integer Linear Program (ILP) formulation; The constraint on line (3) is the same dependency constraint on Formulation 1. 𝜖 𝑖𝑗 and 𝜇 𝑗𝑖 are the overlap variables which ensures the MRT validity through constraints (4) to (10). Constraint (11) links the instructions start time (𝑡 𝑖 ) with their congruence class using a helper variable (𝑦 𝑖 ).…”

“…Two sets of benchmarks are used for the evaluation of the modulo schedulers. The first set, presented in Table 2, is composed of synthetic benchmarks designed to test modulo scheduler algorithms in an HLS environment and were used in [4,26,9,10,5], where the constraints are chosen following [4]. Differently from HLS benchmarks, these codes are composed of a single loop, preventing the hardware inferred for the non-loop parts to influence the loop-related results.…”

“…In this work, we propose to substitute the GA search by a heuristic to construct a solution, which reduces asymptotically the computation time needed to create a loop pipeline, implying in considerable time savings on design-exploration tasks. This paper extends the initial version of this work [10], with a complete evaluation of the proposed approach, including a full description of the method, along with a broad number of examples, and a detailed result analysis over the scheduler impacts on the final hardware quality.…”