Scaling Trends for Dual-Rail Logic Styles Against Side-Channel Attacks: A Case-Study

Nawaz, Kashif; Kamel, Dinal; Standaert, François‐Xavier; Flandre, Denis

doi:10.1007/978-3-319-64647-3_2

Cited by 11 publications

(6 citation statements)

References 34 publications

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“…Feature Size. A common issue encountered in the side-channel literature is the scaling of attacks and countermeasures as devices become more complicated and feature size decreases [22,30,32]. This section uses our simple leakage model to describe the effect of feature size on SCA.…”

Section: Measurement Grid Dimensionmentioning

confidence: 99%

Location, Location, Location: Revisiting Modeling and Exploitation for Location-Based Side Channel Leakages

Andrikos

Batina

Chmielewski

et al. 2019

Lecture Notes in Computer Science

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This publication is distributed under the terms of Article 25fa of the Dutch Copyright Act (Auteurswet) with explicit consent by the author. Dutch law entitles the maker of a short scientific work funded either wholly or partially by Dutch public funds to make that work publicly available for no consideration following a reasonable period of time after the work was first published, provided that clear reference is made to the source of the first publication of the work. This publication is distributed under The Association of Universities in the Netherlands (VSNU) 'Article 25fa implementation' pilot project. In this pilot research outputs of researchers employed by Dutch Universities that comply with the legal requirements of Article 25fa of the Dutch Copyright Act are distributed online and free of cost or other barriers in institutional repositories. Research outputs are distributed six months after their first online publication in the original published version and with proper attribution to the source of the original publication.You are permitted to download and use the publication for personal purposes. Please note that you are not allowed to share this article on other platforms, but can link to it. All rights remain with the author(s) and/or copyrights owner(s) of this work. Any use of the publication or parts of it other than authorised under this licence or copyright law is prohibited. Neither Radboud University nor the authors of this publication are liable for any damage resulting from your (re)use of this publication.If you believe that digital publication of certain material infringes any of your rights or (privacy) interests, please let the Library know, stating your reasons. In case of a legitimate complaint, the Library will make the ma terial

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Section: Measurement Grid Dimensionmentioning

confidence: 99%

Location, Location, Location: Revisiting Modeling and Exploitation for Location-Based Side Channel Leakages

Andrikos

Batina

Chmielewski

et al. 2019

Lecture Notes in Computer Science

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“…The hiding countermeasures are difficult to implement since strict requirements such as aligned signal propagation and balanced routing are difficult to achieve at advanced technology nodes due to the increase in parasitic effects [3]. An efficient preprocessing and machine learning technique can reveal the information from an encryption device designed with weak countermeasures.…”

Section: Introductionmentioning

confidence: 99%

Exploiting On-Chip Voltage Regulators for Leakage Reduction in Hardware Masking

Seçkiner

Köse

2022

Sensors

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A design space exploration of the countermeasures for hardware masking is proposed in this paper. The assumption of independence among shares used in hardware masking can be violated in practical designs. Recently, the security impact of noise coupling among multiple masking shares has been demonstrated both in practical FPGA implementations and with extensive transistor level simulations. Due to the highly sophisticated interactions in modern VLSI circuits, the interactions among multiple masking shares are quite challenging to model and thus information leakage from one share to another through noise coupling is difficult to mitigate. In this paper, the implications of utilizing on-chip voltage regulators to minimize the coupling among multiple masking shares through a shared power delivery network (PDN) are investigated. Specifically, different voltage regulator configurations where the power is delivered to different shares through various configurations are investigated. The placement of a voltage regulator relative to the masking shares is demonstrated to a have a significant impact on the coupling between masking shares. A PDN consisting of two shares is simulated with an ideal voltage regulator, strong DLDO, normal DLDO, weak DLDO, two DLDOs, and two DLDOs with 180∘ phase shift. An 18 × 18 grid PDN with a normal DLDO is simulated to demonstrate the effect of PDN impedance on security. The security analysis is performed using correlation and t-test analyses where a low correlation between shares can be inferred as security improvement and a t-test value below 4.5 means that the shares have negligible coupling, and thus the proposed method is secure. In certain cases, the proposed techniques achieve up to an 80% reduction in the correlation between masking shares. The PDN with two DLDOs and two-phase DLDO with 180∘ phase shift achieve satisfactory security levels since t-test values remain under 4.5 with 100,000 traces of simulations. The security of the PDN improves if DLDO is placed closer to any one of the masking shares.

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“…DPLs aim to balance the switching activity factor for each gate in a design in order to deploy an overall power consumption that is independent from processed data by means of differential gates and (differential) Return-to-Zero (RTZ) encoding. Common DPLs that have been investigated in the literature to decorrelate the power consumption from manipulated data include Wave Dynamic Differential Logic (WDDL) [5], Masked DPL (MDPL) [6], Dynamic and Differential Swing-Limited Logic (DDSLL) [7] and Sense Amplifier Based Logic (SABL) [8].…”

Section: Introductionmentioning

confidence: 99%

SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks

2021

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With the continuous scaling of CMOS technology, which has now reached the 3 nm node at production level, static power begins to dominate the power consumption of nanometer CMOS integrated circuits. A novel class of security attacks to cryptographic circuits which exploit the correlation between the static power and the secret keys was introduced more than ten years ago, and, since then, several successful key recovery experiments have been reported. These results clearly demonstrate that attacks exploiting static power (AESP) represent a serious threat for cryptographic systems implemented in nanometer CMOS technologies. In this work, we analyze the effectiveness of the Standard Cell Delay-based Precharge Logic (SC-DDPL) style in counteracting static power side-channel attacks. Experimental results on an FPGA implementation of a compact PRESENT crypto-core show that the SC-DDPL implementation allows a great improvement of all the security metrics with respect to the standard CMOS implementation and other state-of-the-art countermeasures such as WDDL and MDPL.

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Scaling Trends for Dual-Rail Logic Styles Against Side-Channel Attacks: A Case-Study

Cited by 11 publications

References 34 publications

Location, Location, Location: Revisiting Modeling and Exploitation for Location-Based Side Channel Leakages

Location, Location, Location: Revisiting Modeling and Exploitation for Location-Based Side Channel Leakages

Exploiting On-Chip Voltage Regulators for Leakage Reduction in Hardware Masking

SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks

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