Scaling to the end of silicon with EDGE architectures

Burger, Doug; Keckler, Stephen W.; McKinley, Kathryn S.; Dahlin, Mike; John, Lizy K.; Lin, Calvin; Moore, Charles R.; Burrill, James; McDonald, Robert; Yoder, W.

doi:10.1109/mc.2004.65

Cited by 287 publications

(178 citation statements)

References 13 publications

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“…In order to scale the number of cores in a CMP above this barrier, and into the numbers of cores proposed for tiled architectures [4,6,19,28,29], it is necessary to resort to scalable (i.e., point-to-point) interconnect types. Such interconnects are suitable not only because their peak bandwidth naturally scales with the number of cores, but also because, due to the short-length wires and low radix, their area overhead is a fixed, independent fraction of the number of cores.…”

Section: Current Cmps and Coherence Mechanismsmentioning

confidence: 99%

“…There have been several proposals for tiled CMP architectures [4,6,19,28,29]. Most of these have focused on novel execution paradigms to exploit ILP and DLP in singlethreaded applications.…”

Section: Related Workmentioning

confidence: 99%

“…Either access latencies have to be significantly stretched or the area required by the interconnects has to be increased to the point of becoming impractical. Tiled CMPs [4,6,19,28,29] have been advocated as a possible alternative. Such systems are built from a relatively large number (≥ 32) of relatively simple cores plus a tightly integrated and lightweight point-to-point interconnect.…”

Section: Introductionmentioning

confidence: 99%

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An OS-based alternative to full hardware coherence on tiled CMPs

Fensch

Cintra

2008

2008 IEEE 14th International Symposium on High Performance Computer Architecture

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The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling to a larger number of cores. Tiled CMPs offer better scalability by integrating relatively simple cores with a lightweight point-to-point interconnect. However, such interconnects make snooping impractical and, thus, require alternative solutions to cache coherence. This paper proposes a novel, cost-effective mechanism to support shared-memory parallel applications that forgoes hardware maintained cache coherence. The proposed mechanism is based on the key ideas that mapping of lines to physical caches is done at the page level with OS support and that hardware supports remote cache accesses. It allows only some controlled migration and replication of data and provides a sufficient degree of flexibility in the mapping through an extra level of indirection between virtual pages and physical tiles.We evaluate the proposed tiled CMP architecture on the Splash-2 scientific benchmarks and ALPBench multimedia benchmarks against one with private caches and a distributed directory cache coherence mechanism. Experimental results show that the performance degradation is as little as 0%, and 16% on average, compared to the cache coherent architecture across all benchmarks for 16 and 32 processors.

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Section: Current Cmps and Coherence Mechanismsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An OS-based alternative to full hardware coherence on tiled CMPs

Fensch

Cintra

2008

2008 IEEE 14th International Symposium on High Performance Computer Architecture

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“…Tiled architectures, such as TRIPS, WaveScalar and RAW [1][2] [3] exhibit very promising characteristics in that respect -namely, their decentralized organization eliminates several key scalability bottlenecks found in conventional superscalar processors, and reduces overall circuit complexity, effective wire delays and verification effort [4] [5]. These favorable characteristics make tiled architectures highly relevant to the future of high performance computing.…”

Section: Introductionmentioning

confidence: 99%

“…Large machines, exploiting the huge numbers of raw transistors, possible to integrate in future silicon technologies, can be built in a scalable way, by simply instantiating many such basic tiles on a processor's chip, and then hierarchically organizing them in a suitable way, see e.g. [1] [2][3] [6]. Aggressive instruction-level parallelism (ILP) extraction is key to the performance of tiled architectures, including WaveScalar, TRIPS, and RAW.…”

Section: Introductionmentioning

confidence: 99%

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

Farooq

John

Jacome

2009

High Performance Embedded Architectures and Compilers

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Abstract. Traditional predicated execution uses two techniques: top predication -in which only the head of the dependence chain is predicated, and bottom predication -in which only the tail of the dependence chain is predicated. Top predication prevents speculative execution, thus delivering minimum performance at minimum energy cost, while bottom predication allows full speculation of the dependence chain, resulting in maximum performance at maximum energy cost. In this paper, we propose a novel power-aware ILP extraction technique, denoted the 'elasticblock', that combines these two extremes, exposing superior energy vs. performance trade-offs. Each instruction in the elastic-block is explicitly guarded by two predicates: the speculative, and the final. Instruction's final predicate is generated using traditional if-conversion technique, while the speculative predicate has its default value statically assigned by the compiler, enabling it to make power-performance trade-offs in the code. Several energy saving code optimizations are proposed for the elasticblock structure.

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Dataflow Computers: Their History and Future

Hurson

Kavi

2007

Wiley Encyclopedia of Computer Science and Engineering

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The dataflow model of computation offers an attractive alternative to control‐flow in extracting parallelism from programs. The execution of a dataflow instruction is based on the availability of its operand(s); hence, the synchronization of parallel activities is implicit in the dataflow model. Instructions in dataflow model do not impose any constraints on sequencing except for the data dependencies in the program. The elegant representation of concurrency in dataflow computation led to considerable interest in dataflow modes over the past three decades. These efforts have led to successively more elaborate architechtural implementations of the model. However, studies form past projects have revealed a number of inefficiencies in dataflow computing. Recent advances that may address these deficiencies have generated a renewed interest in dataflow. In this article we will survey the various issues and developments in dataflow computing.

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Scaling to the end of silicon with EDGE architectures

Abstract: The TRIPS architecture is the first instantiation of an EDGE instruction set, a new, post-RISC class of instruction set architectures intended to match semiconductor technology evolution over the next decade, scaling to new levels of power efficiency and high performance.

Cited by 287 publications

References 13 publications

An OS-based alternative to full hardware coherence on tiled CMPs

An OS-based alternative to full hardware coherence on tiled CMPs

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

Dataflow Computers: Their History and Future

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