Scaling superconducting quantum chip with highly integratable quantum building blocks

Abstract

Designing and fabricating large-scale superconducting quantum chips with increasing number of qubits is a pressing challenge for the quantum computing. Here, we propose a 3D stacked chip architecture comprised with quantum building blocks. In which, two primary types of blocks are the qubit block and the coupling block. They are designed as functional parts those can be utilized within the same footprint across multiple levels of the chip stack in the vertical direction. Common technological problems, such as the sensitivity of capacitors and coupling strengths to fabrication parameters, and dielectric losses from interfaces, can be addressed at the intra-block or block level efficiently. Once a library of standard blocks is designed and verified, they can be selected and arranged into arrays on chips at the placing stage of the design flow for specific quantum applications. Such chip structure and design protocol will reduce the design difficulty, and promote the reuse of standard blocks, thus paving the way for chips for noisy intermediate-scale quantum computing and quantum error correction.

Optimize Purcell filter design for reducing influence of fabrication variation

“…The calculation results reveal that the capacitance sensitivity to pattern edge etching deviations is about 4.5 fF/µm. [22] In the related experiments, the actual finger width is measured to be in a range between 4.8 µm and 5.4 µm. The combination of these calculation results and experimental measurements indicate that the fabrication process can result in a maximum deviation of 5.4 fF in the actual capacitance, potentially significantly affecting device performance.…”