2023
DOI: 10.1021/acs.nanolett.3c00031
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Scaling of MoS2 Transistors and Inverters to Sub-10 nm Channel Length with High Performance

Abstract: semiconductors such as monolayer molybdenum disulfide (MoS 2 ) are promising building blocks for ultrascaled field effect transistors (FETs), benefiting from their atomic thickness, dangling-bond-free flat surface, and excellent gate controllability. However, despite great prospects, the fabrication of 2D ultrashort channel FETs with high performance and uniformity remains a challenge. Here, we report a self-encapsulated heterostructure undercut technique for the fabrication of sub-10 nm channel length MoS 2 F… Show more

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Cited by 12 publications
(7 citation statements)
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“…We further examined the drain-induced barrier lowering (DIBL), a key parameter to characterize the immunity of the FET to the SCE Figure c exhibits the threshold voltage ( V th ) as a function of V DS .…”
Section: Results and Discussionmentioning
confidence: 99%
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“…We further examined the drain-induced barrier lowering (DIBL), a key parameter to characterize the immunity of the FET to the SCE Figure c exhibits the threshold voltage ( V th ) as a function of V DS .…”
Section: Results and Discussionmentioning
confidence: 99%
“…Figure c exhibits the threshold voltage ( V th ) as a function of V DS . We extracted a DIBL value of about 333 mV/V using the formula DIBL = prefix− V th high V th low V DS high V DS low , where V th high and V th low are the threshold voltages at V DS high = 1 V and V DS low = 0.1 V, respectively. The obtained DIBL of the vertical FET is relatively satisfactory compared with those of the reported MoS 2 FETs with nanoscale channel length (Table ), indicating that the as-fabricated vertical device structure has better immunity to the SCE.…”
Section: Results and Discussionmentioning
confidence: 99%
See 1 more Smart Citation
“…[49] As V DS increases from 0.25 to 2 V, V T shifts from 0.398 to 0.377 V, which implies that the transistor DIBL is ultralow with 12 mV V −1 , outperforming that of most reported 2D FETs. [50][51][52] Detailed calculations for V T and DIBL are shown in Figure S6 (Supporting Information). It is noteworthy that the off-state current (I OFF ) is maintained in the range of 0.22 to 0.44 pA, much smaller than that in planar 2D-FETs.…”
Section: Device Scheme and Characterizationmentioning
confidence: 99%
“…In recent years, two-dimensional (2D) semiconductors have become one of the focuses of international academics due to their ultrathin thickness, atomic-level flatness, and superior electronic properties. Such features make 2D semiconductors possess natural advantages in minimizing SCEs and solving the critical issues encountered in scaling three-dimensional (3D) bulk semiconductors. The realization of 2D transistors with high mobility, low contact resistance ( R c ), and near-Boltzmann-limit subthreshold swing (SS) demonstrates their great potential in achieving low-power integrated circuits. ,, For example, Intel explored 2D transistor scaling down to a Source-to-Drain contact spacing of 25 nm, comparable to state-of-the-art Si technology . In work led by TSMC, Wu et al demonstrated contact length scaling down to 30 nm with a low contact resistance of sub-100 Ω μm for monolayer MoS 2 channel transistors .…”
Section: Introductionmentioning
confidence: 99%