Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm

Stillmaker, Aaron; Baas, Bevan M.

doi:10.1016/j.vlsi.2017.02.002

Cited by 278 publications

(145 citation statements)

References 20 publications

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“…Stillmaker et al presented in Ref. [4] scaling equations for all CMOS technologies starting from 180 nm down to 7 nm. They did extensive spice simulations and produced equations to calculate the delay of any node based on the delay of the previous node using their scaling equation.…”

Section: Related Workmentioning

confidence: 99%

“…The other traditional gains, such as increasing the switching speed and lowering the supply voltage to improve power consumption, are no longer sustainable. [1][2][3][4] Beyond 32 nm, the conventional planar CMOS transistors also suffered from high variability and performance degradation. 5 During the process of attempting to improve transistor performance, the double-gated transistors showed good potential towards improving the switching strength and hence the performance of the transistor.…”

Section: Introductionmentioning

confidence: 99%

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System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation

Majzoub¹,

Taouil²,

Hamdioui³

2019

Journal of Low Power Electronics

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Standard low power design utilizes a variety of approaches for supply and threshold control to reduce dynamic and idle power. At a very early stage of the design cycle, the V dd and V th values are estimated, based on the power budget, and then used to scale the delay and estimate the design performance. Furthermore, process variation in sub-20 nm feature technologies introduces a substantial impact on speed and power. Thus, the impact of such variation on the scaled delay has to also be considered in the performance estimation. In this paper, we propose a system-level model to estimate this delay, taking into consideration voltage scaling under within-die process variation for both planar and FinFET CMOS transistors in the sub-20 nm regime. The model is simple, has acceptable accuracy and is particularly useful for architectural-level simulations for lowpower design exploration at an early stage in the design space exploration. The proposed model estimates the delay in different supply voltage and threshold voltage ranges. The model uses a modified alpha-power equation to measure the delay of the critical path of a computational logic core. The targeted technology nodes are 14 nm, 10 nm, and 7 nm for FinFETs, and 22 nm, and 16 nm for planar CMOS. Within-die process variation is assumed to be lumped in with the threshold voltage and the transistor channel length and width to simplify its impact on delay. For the given technology nodes, the average percentage error numbers of theproposed delay equation compared to hSpice are between 0.5% to 14%.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation

Majzoub¹,

Taouil²,

Hamdioui³

2019

Journal of Low Power Electronics

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“…According to have a fair comparison, the operational frequency can be normalized by the CMOS technology. The delay information for the 180 nm, 130 nm, and 90 nm [16], which are 77.2 ps, 34.7 ps, and 26.5 ps for an inverter delay, is used to normalize the frequency. Thus, the definition of the frequency normalized function is expressed as follows.…”

Section: Comparison To Existing Workmentioning

confidence: 99%

“…Freq n = Freq w × Delay w Delay 90 nm (16) where the Freq n indicates the operational frequency normalized to 90 nm technology, and Freq w is the operational frequency that want to be normalized. The Delay 90 nm and Delay w are the inverter delay time for the 90 nm and the technology which want to be normalized, respectively.…”

Section: Comparison To Existing Workmentioning

confidence: 99%

Cost-effective multi-standard video transform core using time-sharing architecture

Tseng

Chen

2019

EURASIP J. Adv. Signal Process.

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This paper presents a cost-effective two-dimensional (2-D) inverse discrete cosine transform (IDCT) for supporting multiple standards of MPEG 1/2/4, H.264, VC-1, and HEVC. The proposed approach employs a time allocation scheme to enable the simultaneous processing of the first and second dimensions in order to enhance data throughput and attain hardware utilization of 100%. The proposed one-dimensional (1-D) IDCT uses distributed arithmetic (DA) in conjunction with factor sharing (FS) within a hardware sharing architecture. Four parallel computation streams are employed to enhance the throughput rate as four times of operation frequency. The efficacy of this approach was verified by fabricating a test chip using the Taiwan Semiconductor Manufacturing Company Limited (TSMC) 90 nm Complementary Metal-Oxide-Semiconductor (CMOS) process. The inverse transform core has an operating frequency of 200 MHz and a throughput of 800 M-pels/s with a gate count of 27.2 K.

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“…Table I gives the comparison between other recent works and the proposed architectures at the 32-bit counters option. In the table, to make a fair comparison, the F Max results of [13] and [14], which were respectively built on a 65 nm FPGA and a 40 nm FPGA, were scaled into equivalent 20 nm chips' performances by using the scaling equations from work [15]. After that, their MIPS results were also scaled proportionally according to their scaled F Max values.…”

Section: Fic Core Modulementioning

confidence: 99%

Frequent items counter based on binary decoders

Inoue

Hoang

Pham

2018

IEICE Electron. Express

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In this paper, the hardware design of frequent items counter is proposed. The key idea is to create a matrix of binary-value by using an array of binary-decoder to decode all of the input items in parallel. After that, an array of population-count modules are applied to the rows of the matrix to generate counting results. The architecture was implemented with five options of bit/item from 6-bit/item to 10-bit/item, and seven options of count-register bit-width from 8-bit counters to 32-bit counters. Therefore, there were 35 different versions of implementation presented in this paper. Those implementations were built on the Field-Programmable Gate Array (FPGA) board of Altera Arria V SoC development kit. Also, they were synthesized to chips with the process technology of 65 nm Silicon On Thin Buried-Oxide (SOTB). The experimental results of the proposed architecture achieved outstanding timing performances compared to other attempts to date.

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Scaling equations for the accurate prediction of CMOS device performance from 180 nm to 7 nm

Cited by 278 publications

References 20 publications

System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation

System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation

Cost-effective multi-standard video transform core using time-sharing architecture

Frequent items counter based on binary decoders

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