Scaling consideration of BiCMOS SRAMs

Abstract

This paper presents scaling consideration of BiCMOS SRAMs based on an experimental 4K ECL 1/0 BiCMOS SRAM design. According to analysis, further integration of the BiCMOS SRAMs over lMbits is limited by the evolution of the CMOS processing technology and the BiCMOS circuit design techniques, and BiCMOS circuits shrink the access time without a power penalty.S u m m a r y Recently, BiCMOS technology has been becoming one of the major VLSI technologies. BiCMOS SRAMs, combining CMOS memory cells, bipolar sense amps and ECL 1/0 buffers, have shown their capabilities for high-speed and large-size memory applications. Scaling of CMOS technologies, devices, and SRAM circuits has been intensively reported. Scaling of bipolar ECL devices and circuits has also been discussed. However, there are few reports on scaling consideration of BiCMOS devices and SRAM circuits. In this paper, scaling of the BiCMOS SRAMs will be described. Fig. 1 shows the performance of the recent BiCMOS, CMOS, and ECL SRAMs in terms of per-bit power access time product as a function of size of integration. For CMOS SRAMs, the per-bit power access time product has decreased from 20fJ/bit for a 64K SRAM to 7fJ/bit for a 1M SRAM. For ECL SRAMs, the per-bit power access time product stays around 1000fJ/bit for below-256K SRAMs. As for BiCMOS SRAMs, the per-bit consumed energy is between CMOS and ECL ones. The continuing reduction on the per-bit consumed energy for the CMOS and BiC-MOS SRAMs is owing to the scaling of the CMOS technology. As a matter of fact, the per-bit consumed energy of the recent BiCMOS SRAMs is close to CMOS ones as a result of the dominance of the CMOS memory cell array in a SRAM chip. On the other hand, as shown in Fig. 2, the access time of the BiCMOS SRAM, which is comparable to ECL one, is much smaller as compared to CMOS one. Consequently, the BiCMOS SRAM has the ECL speed and the CMOS low power capabilities. In order to investigate the role of the BiCMOS circuit techniques using scaled BiC-MOS technology, Figs., 1 and 2 have been reorganized as shown in Figs. 3 and 4. The normalized per-bit consumed energy is defined as the per-bit power access time product divided by the square of the basic unit of the design rule, e.g. L=1.2 for the 4K SRAM [14] using a 1.2prn BiCMOS technology. Using the normalized per-bit consumed energy definition, the figure-of-merit of each SRAM can be evaluated in terms of the circuit performance only, excluding the benefits coming from the technology scaling. As shown in Fig. 4, the normalized access time, which is defined as the access time divided by the basic unit of the design rule, for the CMOS SRAM increases for every SRAM generation. On the other hand, the normalized access time of the BiC-MOS SRAM stays about the same, which implies that the bipolar devices have been utilized effectively in the BiC-MOS circuit design. The usefulness of the BiCMOS circuit design techniques is especially visible for large-size SRAMs. Fig. 5 shows the normalized size of a memory cell. For BiCMOS and CMOS SRAMs, ...