Scaling Analysis of Nanoelectromechanical Memory Devices

Nagami, T.; Tsuchiya, Yoshishige; Uchida, Ken; Mizuta, Hiroshi; Oda, Shunri

doi:10.1143/jjap.49.044304

Cited by 10 publications

(3 citation statements)

References 23 publications

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“…The force is sufficiently strong to be considered in a nanometer-scale separation embedded in nanoelectromechanical systems. 3,4) Novel ideas related to this force, such as quantum levitation [5][6][7] and conversion between electrical energy and quantum fluctuation energy in a vacuum, 8) have been proposed. To evaluate the strength of the Casimir forces experimentally, several measurements have been performed in the nanometer-scale over the past decade.…”

Section: Introductionmentioning

confidence: 99%

Measurement of the Casimir force between a spherical gold tip and Si(111)-(7 × 7) surfaces

Yoshida¹,

Higashino²,

Sueoka³

2016

Jpn. J. Appl. Phys.

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Section: Introductionmentioning

confidence: 99%

Measurement of the Casimir force between a spherical gold tip and Si(111)-(7 × 7) surfaces

Yoshida¹,

Higashino²,

Sueoka³

2016

Jpn. J. Appl. Phys.

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“…Finally, the energy required to move the SG is a Fig. 10 Characteristic curve of a transient analysis performed to calculate the mechanical switching time (pull-in effect) of the SG combination between several kinds of energies such as elastic energy E m , kinetic energy E k , damping loss energy E d , electrostatic energy E e and charging loss energy E R [26]. A detailed analysis for energy and power consumption is being processed which results will be included in further publications.…”

Section: Numerical Analysis Of the Suspended Gatementioning

confidence: 99%

Hybrid numerical analysis of a high-speed non-volatile suspended gate silicon nanodot memory (SGSNM)

2011

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We present a hybrid numerical analysis of a high-speed and non-volatile suspended gate silicon nanodot memory (SGSNM) which co-integrates a nano-electromechanical (NEM) control gate with a MOSFET as a readout element and silicon nanodots as a floating gate. A hybrid NEM-MOS circuit simulation is developed by taking account of the pull-in/pull-out operation of the suspended gate and electron tunnelling processes through the tunnel oxide layer as behavioural models. The signals for programming, erasing and reading are successfully achieved at circuit level simulation. The programming and erasing times are found as short as 2.5 nsec for a SGSNM with a 1-µm-long suspended gate, which is a summation of the mechanical pull-in/pullout times and the tunnel charging/discharging times.

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“…Co-integration of NEMS and CMOS devices on the same die, a hybrid NEMS-CMOS approach, has been proposed in [7], [10] and implemented in [11]. Moreover, several groups have performed scaling analysis to identify key challenges of MEMS integration in the future ultra low-power IC design applications [12]- [14].…”

Section: Introductionmentioning

confidence: 99%

A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs

Dadgour

Hussain

Banerjee

2010

Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design

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Nano-Electro-Mechanical Switches (NEMS) offer the prospect of improved energy-efficiency in digital circuits due to their near-zero subthreshold leakage and extremely low subthreshold swing values. Among the different approaches of implementing NEMS, laterallyactuated double-gate NEMS devices have attracted much attention as they provide unique and exciting circuit design opportunities. For instance, this paper demonstrates that compact XOR/XNOR gates can be implemented using only two such NEMS transistors. While this in itself is a major improvement, its implications for minimizing Boolean functions using Karnaugh maps (K-maps) are even more significant. In the standard K-map technique, which is used in digital circuit design, adjacent "1s" (minterms) are grouped only in horizontal and/or vertical directions; the diagonal (or zig-zag) grouping of adjacent "1s" is not an option due to the absence of compact XOR/XNOR gates. However, this work demonstrates, for the first time ever, that in lateral double-gate NEMS-based circuits, grouping of minterms is possible in horizontal and vertical as well as diagonal fashions. This is because the diagonal groupings of minterms require XOR/XNOR operations, which are available in such NEMS-based circuits at minimal costs. This novel design paradigm facilitates more compact implementations of Boolean functions and thus, considerably improves their energy-efficiency. For example, a lateral NEMS-based full-adder is implemented using less than half the number of transistors, which is required by a CMOS-based full-adder. Furthermore, circuit simulations are performed to evaluate the energy-efficiencies of the NEMS-based 32-bit carry-save adders compared to their standard CMOS-based counterparts.

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Scaling Analysis of Nanoelectromechanical Memory Devices

Cited by 10 publications

References 23 publications

Measurement of the Casimir force between a spherical gold tip and Si(111)-(7 × 7) surfaces

Measurement of the Casimir force between a spherical gold tip and Si(111)-(7 × 7) surfaces

Hybrid numerical analysis of a high-speed non-volatile suspended gate silicon nanodot memory (SGSNM)

A new paradigm in the design of energy-efficient digital circuits using laterally-actuated double-gate NEMs

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