Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafers

Duriez, B.; Vellianitis, G.; Dal, M.J.H. van; Doornbos, G.; Oxland, R.; Bhuwalka, K.K.; Holland, M.; Chang, Young-Soo; Hsieh, C.H.; Yin, K.M.; See, Y. C.; Passlack, M.; Diaz, C.H.

doi:10.1109/iedm.2013.6724666

Cited by 39 publications

(26 citation statements)

References 7 publications

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“…A Ge layer with a few hundred nanometers stands on a thick BOX layer, which enables strong two-dimensional optical confinement in the Ge MIR photonic-wire devices. Meanwhile, Ge CMOS transistors, which are expected to be a very promising candidate for future high-performance and low-power LSIs by utilizing high-mobility Ge channel [10][11][12][13][14], can be integrated with the Ge MIR photonics. By choosing BOX materials which are transparent to MIR light such as chalcogenide glass, this platform potentially supports a considerably wide MIR range from 2 to 15 mm where Ge shows good transmission.…”

Section: Introductionmentioning

confidence: 99%

Impact of thermal annealing on Ge-on-Insulator substrate fabricated by wafer bonding

Kang

Takenaka

et al. 2016

Materials Science in Semiconductor Processing

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Section: Introductionmentioning

confidence: 99%

Impact of thermal annealing on Ge-on-Insulator substrate fabricated by wafer bonding

Kang

Takenaka

et al. 2016

Materials Science in Semiconductor Processing

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“…[1][2][3][4][5][6][7] These so-called high mobility materials are implemented in new device concepts and novel architectures, for example tunnel FETs and gate-all-around devices, in order to meet the power and performance requirements. Reference 7 gives an overview of the innovations in materials and new device concepts that will be needed to continue Moore's law to sub-7nm technology nodes.…”

mentioning

confidence: 99%

Processing Technologies for Advanced Ge Devices

Loo

Hikavyy

Witters

et al. 2016

ECS J. Solid State Sci. Technol.

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With the continued scaling of CMOS devices below the 10 nm node, process technologies become more and more challenging as the allowable thermal budget for device processing continuously reduces. This is especially the case during epitaxial growth, where a reduction of the thermal budget is required for a number of potential reasons for example to avoid uncontrolled layer relaxation of strained layers, surface reflow of narrow fin structures, as well as doping diffusion and material intermixing. Further aspects become even more challenging when Ge is used as a high-mobility channel material and when the device concept moves from a FinFET design to a nanowire FET design (also called Gate-All-Around FET). In this contribution we address some of the challenges involved with the integration of high mobility Group IV materials in these advanced device structures.

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“…The Ge FinFET presented in this paper shows the best g m /SS sat ratio of relaxed Ge MuGFET devices reported to date and paves the way for the introduction of Ge as a p-MOS option for future FinFET technologies. Further improvement for the Ge FinFET technology can be expected by introducing channel strain, scaling the thickness of the gate dielectric, and fin width scaling [31].…”

Section: Discussionmentioning

confidence: 99%

“…Short-channel effect (SCE) is apparent in terms of the strong DIBL and V t rollup starting at L G < 110 nm. Improvement of the SCE control can be achieved by scaling the CET and W FIN , which will be demonstrated in [31]. Fig.…”

Section: B Ohmic Contactsmentioning

confidence: 98%

Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping

Dal

Vellianitis

Duriez

et al. 2014

IEEE Trans. Electron Devices

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We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trapassisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at V DS = −0.5 V, good short-channel effect control, and high transconductance (g m = 1.2 mS/µm at V DS = −1 V and 1.05 mS/µm at V DS = −0.5 V for L G = 70 nm). The Ge FinFET presented in this paper exhibits the highest g m /SS sat at V DD = 1 V reported for nonplanar unstrained Ge p-FETs to date.Index Terms-Aspect ratio trapping (ART), band-to-band tunneling (BTBT), epitaxy, FinFET, germanium, scaling, trap-assisted tunneling (TAT).

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Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafers

Cited by 39 publications

References 7 publications

Impact of thermal annealing on Ge-on-Insulator substrate fabricated by wafer bonding

Impact of thermal annealing on Ge-on-Insulator substrate fabricated by wafer bonding

Processing Technologies for Advanced Ge Devices

Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping

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