Scalable Ternary Content Addressable Memory implementation using FPGAs

Jiang, Weirong

doi:10.1109/ancs.2013.6665177

Cited by 72 publications

(66 citation statements)

References 13 publications

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“…All tables (State, Port, SAR) and Timers hold one entry per connection as discussed in section IV, therefore they scale linearly. Further, the session lookup data structure also scales linearly with the number of sessions as has been shown in [20]. Thus, scaling is linear with number of supported sessions and limited by the amount of BRAM inside the FPGA while LUT and FlipFlop usage will remain mostly constant.…”

Section: ) 10 Gbps Line-rate Supportmentioning

confidence: 95%

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Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware

Sidler

Alonso

Blott

et al. 2015

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

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TCP/IP is the predominant communication protocol in modern networks but also one of the most demanding. Consequently, TCP/IP offload is becoming increasingly popular with standard network interface cards. TCP/IP Offload Engines have also emerged for FPGAs, and are being offered by vendors such as Intilop, Fraunhofer HHI, PLDA and Dini Group. With the target application being high-frequency trading, these implementations focus on low latency and support a limited session count. However, many more applications beyond high-frequency trading can potentially be accelerated inside an FPGA once TCP with high session count is available inside the fabric. This way, a network-attached FPGA on ingress and egress to a CPU can accelerate functions such as encryption, compression, memcached and many others in addition to running the complete network stack. This paper introduces a novel architecture for a 10 Gbps linerate TCP/IP stack for FPGAs that can scale with the number of sessions and thereby addresses these new applications. We prototyped the design on a VC709 development board, demonstrating compatibility with existing network infrastructure, operating at full 10 Gbps throughput full-duplex while supporting 10,000 sessions. Finally, the design has been described primarily using high-level synthesis, which accelerates development time and improves maintainability.

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Section: ) 10 Gbps Line-rate Supportmentioning

confidence: 95%

“…At the heart of the lookup problem is a scalable TCAM implementation which is based on a hash table and presented in [20]. In comparison to a traditional TCAM, it uses less resources and scales linearly in its resource requirements with the number of entries.…”

Section: ) Session Lookup Port and State Table Timers And Event Enmentioning

confidence: 99%

Scalable 10Gbps TCP/IP Stack Architecture for Reconfigurable Hardware

Sidler

Alonso

Blott

et al. 2015

2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

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“…One N -bit BV is stored in each RAM, indicating the match condition of the RAM's search key. Such RAM-based lookup mechanism is as efficient as TCAM [10]. …”

Section: B Flow Tablementioning

confidence: 99%

“…However, TCAMs are expensive, power-hungry, and not scalable with respect to clock rate or circuit area [9], [10]. FPGA technologies have become an attractive option for implementing real-time network processing engines [11], [12], [13].…”

Section: Introductionmentioning

confidence: 99%

A flexible and scalable high-performance OpenFlow switch on heterogeneous SoC platforms

Zhou

Jiang

Prasanna

2014

2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC)

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Software Defined Networking (SDN) has been proposed as a flexible solution for the next generation Internet provision. OpenFlow is a pioneering protocol for SDN which enables a hardware data plane to be managed by a softwarebased controller in a standard way. In this paper, we present a hardware-software co-design approach of an OpenFlow switch using a state-of-the-art heterogeneous system-on-chip (SoC) platform. Specifically, we implement the OpenFlow switch on a Xilinx Zynq ZC706 board. The Xilinx Zynq SoC family provides a tight coupling of field programmable gate array (FPGA) fabric and ARM processor cores, making it an attractive on-chip implementation platform for SDN switches. High-performance, yet highly-programmable, data plane processing can reside in programmable logic, while complex control software can reside in ARM processor. Our proposed architecture involves a methodology that scales across: (a) a range of possible packet throughput rates and (b) a range of possible flow table sizes. Post-place-androute results show that our design targeted at Xilinx Zynq can achieve a total 88 Gbps throughput for a 1K flow table which supports dynamic and hitless updates. Correct operation has been demonstrated using a ZC706 board.

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“…14 The 4-port 1 BgE NetFPGA Xilinx Virtex-II Pro 50 has been selected based on the following requirements: a platform capable of supporting high data rates (near-application-specific integrated circuit (ASIC) performance); 11,15 flexible enough to allow the implementation of a completely new core network forward engine. Due to the NetFPGA platform capabilities, it has been used previously to implement an IP-less forwarding fabric named Bloom-filter based.…”

Section: Keyflow and Openflow Implementationmentioning

confidence: 99%