Scalable shared-memory multiprocessor architectures

Thakkar, Shreekant; Dubois, Michel; Laundrie, A.T.; Sohi, Gurindar S.

doi:10.1109/2.55502

Cited by 22 publications

(6 citation statements)

References 10 publications

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“…We further differentiate our design from theirs with the use of on-die point-to-point connections from the core to the L1's to improve latency, the addition of L0 buffers to hide increased L1 access time, and 3D integration to reduce bus latency. Many other researchers have looked at multiple bus systems in both interleaved and non-interleaved architectures [5,10,15,44]. However, none of their work explicitly shows how interleaved busses can be used to scale unmodified coherence protocols.…”

Section: Related Workmentioning

confidence: 99%

XPoint cache

Dreslinski

Manville

Sewell

et al. 2012

Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques

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With multi-core processors now mainstream, the shift to many-core processors poses a new set of design challenges. In particular, the scalability of coherence protocols remains a significant challenge. While complex Network-on-Chip interconnect fabrics have been proposed and in some cases implemented, most of industry has slowly evolved existing coherence solutions to meet the needs of a growing number of cores. Industries' slow adoption of Networkon-Chip designs is in large part due to the significant effort needed to design and verify the system. However, simply scaling bus-based coherence is not straightforward either because of increased contention and latency on the bus for large core counts.This paper proposes a new architecture, XPoint, which does not need to modify existing bus-based snooping coherence protocols to scale to 64 core systems. XPoint employs interleaved cache structures with detailed floorplaning and system analysis to reduce contention at high core counts. Results show that the XPoint system achieves, on average, a 28× and 35× speedup over a single core design on the Splash2 benchmarks for a 32 and 64 core system respectively (a 1.6× improvement over a 64 core conventional bus). XPoint is also evaluated as a 3D stacked system to reduce further bus latency. Results show a 29× and 45× speedup for 32 and 64 core systems respectively (a 2.1× improvement over a 64 core conventional bus and within 8% of the speedup of a 64 core system with an ideal interconnect). Measurements also show that the XPoint system decreases bus contention of a 64 core system to only 13% higher than that of an 8-core design (a 29× improvement over a 64 core conventional bus).

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Section: Related Workmentioning

confidence: 99%

XPoint cache

Dreslinski

Manville

Sewell

et al. 2012

Proceedings of the 21st International Conference on Parallel Architectures and Compilation Techniques

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show abstract

“…However, the shared-memory shared-bus configuration also suffers a serious deficiency of very limited scalability, generally up to 10 to 20 CPUs, due to limited bandwidth of the shared bus. Since everincreasing processing power is in demand for large database/knowledgebase computing and transaction processing, design of highly scalable multiprocessors is of great significance and interest to computer architects [1]. Motivated by this observation, we started the M 2 hierarchical multiprocessor project in Spring 1991.…”

Section: Introductionmentioning

confidence: 99%

The M2 hierarchical multiprocessor

Oyang

Sheu

Cheng

et al. 1993

Future Generation Computer Systems

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“…The first bus-based multiprocessor with snooping caches was the Synapse N+1 described by Frank [5] . Agarwal [6] first described the idea of distributing directories with the memories to obtain a scalable implementation of cache coherence, which was served as the basis of the Standford DASH multiprocessor [7] . The commercial scalable coherent shared memory was implemented in Kendall Square Research KSR-1 in 1992 [8] .…”

Section: Evolution Of Cache Coherence Protocolsmentioning

confidence: 99%

Cache Coherence Protocols in Shared-Memory Multiprocessors

Lian¹,

Ning²,

Xie³

et al. 2015

Advances in Computer Science Research

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Abstract. This paper is a review of the recent research about the design of cache coherence protocols in shared-memory multiprocessors. Two important aspects of shared memory systems are memory consistency and cache coherence. Two major available protocols for cache coherence problems are snoopy coherence and directory based coherence. The snoopy cache protocol is simple and easy to implement, but relies on a low-latency, shared interconnection among the processors and the memory modules. The directory-based multiprocessors communicate with a common directory whenever the processor's action may cause an inconsistency between its cache and the other caches or memory. No broadcast is necessary in this case and therefore the network medium may be of almost any kind. However, the overhead of directory maintenance and look-up time plus the high-latency of communication networks make the directory scheme unattractive. To prevent the directory from becoming the bottleneck, directory entries can be distributed along with the memory, so that different directory accesses can go to different locations.

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Scalable shared-memory multiprocessor architectures

Cited by 22 publications

References 10 publications

XPoint cache

XPoint cache

The M2 hierarchical multiprocessor

Cache Coherence Protocols in Shared-Memory Multiprocessors

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