Scalable power control for many-core architectures running multi-threaded applications

Abstract

Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cannot scale well with the rapidly increasing level of core integration. While a few recent studies propose power control algorithms for many-core architectures, those solutions assume that the workload of every core is independent and therefore cannot effectively allocate power based on thread criticality to accelerate multi-threaded parallel applications, which are expected to be the primary workloads of many-core architectures. This paper presents a scalable power control solution for many-core microprocessors that is specifically designed to handle realistic workloads, i.e., a mixed group of single-threaded and multi-threaded applications. Our solution features a three-layer design. First, we adopt control theory to precisely control the power of the entire chip to its chip-level budget by adjusting the aggregated frequency of all the cores on the chip. Second, we dynamically group cores running the same applications and then partition the chip-level aggregated frequency quota among different groups for optimized overall microprocessor performance. Finally, we partition the group-level frequency quota among the cores in each group based on the measured thread criticality for shorter application completion time. As a result, our solution can optimize the microprocessor performance while precisely limiting the chip-level power consumption below the desired budget. Empirical results on a 12-core hardware testbed show that our control solution can provide precise power control, as well as 17% and 11% better application performance than two state-of-the-art solutions, on average, for mixed PARSEC and SPEC benchmarks. Furthermore, our extensive simulation results for 32, 64, and 128 cores, as well as overhead analysis for up to 4,096 cores, demonstrate that our solution is highly scalable to many-core architectures.

Hierarchical power budgeting for Dark Silicon chips

“…Adjustment of power/frequency of individual cores within the cluster, depending upon the input data and power consumption (lines [10][11][12]. The voltage of the cores is scaled accordingly.…”

“…Further, at any time instance, the summation of powers of all clusters will result in power ptot. Note that our Inter-cluster power distribution is different than the control based power adjustment approach discussed in [10], which requires a feedback loop and a tuning parameter.…”

“…PEPON [9] also presents a two-level power budgeting scheme to maximize performance within the allocated power cap. The scheme in [10] targets control-based chip level and application level power budgeting, while accounting for the critical threads of the application. These scheme do not consider (1) resource allocation (i.e.…”

An Analytical Framework for Estimating Scale-Out and Scale-Up Power Efficiency of Heterogeneous Manycores

“…A large body of previous work only applies on homogenous architectures [9] [10]. For example, CP R (Composable Performance Regression) [11] predicts the performance of homogeneous multi-core architecture, but is unable to be applied to heterogeneous architectures.…”

Correction prediction: Reducing error correction latency for on-chip memories

“…One simple, yet effective, technique to reduce the power of on-chip memories (e.g., caches) is voltage scaling [21], [20], [28], [32], [10]. Reducing the supply voltage results in significant reductions in static and dynamic power [32].…”