Scalable platform for adaptive optics real-time control, part 2: field programmable gate array implementation and performance

Abstract

The next generation of Adaptive Optics (AO) systems on large telescopes will require immense computation performance and memory bandwidth, both of which are challenging with the technology available today. The objective of this work is to create a future-proof adaptive optics platform on an FPGA architecture, which scales with the number of subapertures, pixels per subaperture and external memory. We have created a scalable adaptive optics platform with an off-the-shelf FPGA development board, which provides an AO reconstruction time only limited by the external memory bandwidth. SPARC uses the same logic resources irrespective of the number of subapertures in the AO system. This paper is aimed at embedded developers who are interested in the FPGA design and the accompanying hardware interfaces. The central theme of this paper is to show how scalability is incorporated at different levels of the FPGA implementation. This work is a continuation of Part 1 of the paper which explains the concept, objectives, control scheme and method of validation used for testing the platform.

Scalable platform for adaptive optics real-time control, part 1: concept, architecture, and validation

“…More details on the BRAM addressing is specified in Surendran et al 25 and Part 2 22 of the paper. The speed of slope computation is determined by the amount of logic resources on the FPGA.…”

“…The details on how the memory speed adaptability and scalability is implemented in the AO reconstructor, is discussed in part 2 22 of the paper.…”

“…This part is intended for astronomers and the user community who are primarily interested in understanding the capabilities and performance results of SPARC. Part 2 22 describes in depth, the implementation of SPARC on an off-the-shelf Field Programmable Gate Array (FPGA) development board. Part 2 22 contains the details of how scalability and adaptability has been built into SPARC in the memory interface and in the reconstruction matrix.…”

“…Part 2 22 describes in depth, the implementation of SPARC on an off-the-shelf Field Programmable Gate Array (FPGA) development board. Part 2 22 contains the details of how scalability and adaptability has been built into SPARC in the memory interface and in the reconstruction matrix. It also explains the different techniques of AO reconstruction with their own levels of computational power required per degrees of freedom.…”

“…It also explains the different techniques of AO reconstruction with their own levels of computational power required per degrees of freedom. Part 2 22 is aimed at embedded system developers interested in the design of a scalable AO real-time controller on an FPGA. Section 2 of this paper explains the objectives and the levels of scalability that is implemented on SPARC.…”