Scalable Packet Classification on FPGA

Jiang, Weirong; Prasanna, Viktor K.

doi:10.1109/tvlsi.2011.2162112

Cited by 120 publications

(61 citation statements)

References 25 publications

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“…The design uses 5-tuple rule sets, where the maximum achievable throughput can be even 100 Gbps. [7] presents a 12-tuple based packet classification system, where the architecture is a multi-pipeline, decision tree based design. The maximum achievable throughput is 80 Gbps, in a case of a minimum sized packets.…”

Section: Related Workmentioning

confidence: 99%

Line-rate packet processing in hardware: the evolution towards 400 Gbit/s

Tóthfalusi¹,

Orosz

2015

Proceedings of the 9th International Conference on Applied Informatics, Volume 1

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Network packet parsing and packet forwarding are general tasks for all routing devices. However, the requirement for line-rate packet processing, independently from the transmission technology, is a common demand against core network equipments. In this paper, we investigate programmable hardware architectures (i.e., Field Programmable Gate Array -FPGA) as central building blocks of the data plane for state-of-the-art 100 Gbit/s network devices. We reveal the benefits and drawbacks of the available hardware architectures (such as Network Processors, Application-Specific Integrated Circuits (ASIC) and FPGAs, respectively). After showing the general packet processing steps on programmable hardware, we describe the problem space of line-rate packet processing in relation to the evolution of transmission technologies, i.e., 1, 10, 100 Gbit/s Ethernet and beyond. Moreover, we present design trade-offs, such as operational frequency, data path width and resource requirement, covering the 1 to 400 Gbit/s throughput range and we propose best practices for their hardware designs.

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Section: Related Workmentioning

confidence: 99%

Line-rate packet processing in hardware: the evolution towards 400 Gbit/s

Tóthfalusi¹,

Orosz

2015

Proceedings of the 9th International Conference on Applied Informatics, Volume 1

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“…According to the targeted platforms, algorithmic solutions for packet classification can be categorized into hardware-based approaches and software-based approaches. The hardware-based approaches usually exploit FPGA [6] or GPU [13] platforms. For large rule sets, external memory is often used; the low access rate and long access latency of external memory limit the performance for these approaches.…”

Section: Related Workmentioning

confidence: 99%

“…Many hardware-based packet classification approaches [6], [13] ignore the host-to-device transfer time when processing packets. Considering this I/O overhead, for example, a throughput of 2 MPPS can be achieved using GPU coprocessors for 5-field packet classification [13].…”

Section: F Comparison With Prior Workmentioning

confidence: 99%

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Performance modeling and optimizations for decomposition-based large-scale packet classification on multi-core processors

Zhou

Prasanna

2014

2014 IEEE 15th International Conference on High Performance Switching and Routing (HPSR)

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Abstract-Large-scale packet classification such as OpenFlow table lookup in Software Defined Networking (SDN) is a key task performed at the Internet routers. However, the increasing size of the rule set and the increasing width of each individual rule make large-scale packet classification a challenging problem. In this paper, we present a decompositionbased approach for large-scale packet classification on multicore processors. We develop a model to predict the performance of the classification engine with respect to throughput and latency. This model involves the architectural parameters of the multi-core processors and the design requirements of packet classification. Based on this model, we employ optimization techniques such as grouping short fields in the search phase and early termination of the merge phase. The performance model can be applied to other generic multi-field classification problems as well. To evaluate the accuracy of the performance model, we implement a 15-field classification engine on stateof-the-art multi-core processors. Experimental results show that, the proposed model predicts the performance with less than ±10% error. For a 32 K 15-field rule set, the optimized decomposition-based approach achieves 2000 ns per packet latency and 33 Million Packets Per Second (MPPS) throughput (49% of the peak throughput). The peak performance assumes an ideal execution model that uses an optimized execution sequence and ignores memory access latency, data dependencies, and context switch overhead.

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“…In packet classification, the techniques include [3] for example, ternary content addressable memory (TCAM)-based packet classification, Bloom filter-based packet classification and decision tree-based packet classification. In pattern matching, the technique includes for example, fixed string-based pattern matching and regular expression-based pattern matching.…”

Section: Introductionmentioning

confidence: 99%

The Investigation and Development Status of Deep Packet Inspection

Zheng¹,

Cao²,

Gao³

et al. 2017

dtcse

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Abstract. The network security is an important issue in the Development of the Internet of Things (IoT). For detecting and defending the network attacks, the deep packet inspection is a promising technology that attracts the research and development attentions from the universities and industries. This paper overviews the investigations and development status of the deep packet inspection technology and summarizes different deep packet inspection techniques. Moreover, the paper also presents our investigations on the deep packet inspection and the related works.

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Scalable Packet Classification on FPGA

Cited by 120 publications

References 25 publications

Line-rate packet processing in hardware: the evolution towards 400 Gbit/s

Line-rate packet processing in hardware: the evolution towards 400 Gbit/s

Performance modeling and optimizations for decomposition-based large-scale packet classification on multi-core processors

The Investigation and Development Status of Deep Packet Inspection

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