Scalable Nonlinear FET Model Based on a Distributed Parasitic Network Description

Resca, Davide; Santarelli, Alberto; Raffo, Antonio; Cignani, Rafael; Vannini, G.; Filicori, F.; Schreurs, Dominique

doi:10.1109/tmtt.2008.918153

Cited by 48 publications

(28 citation statements)

References 34 publications

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“…The intrinsic portion of a standard two-finger test HEMT is extracted with a combination of an extended form of the EM extrinsic treatment in [3][4][5] for a single gate finger and the robust extraction technique of [6].…”

Section: Device Deconstructionmentioning

confidence: 99%

“…Ports 1 and 2 are the external measurement ports, while internal ports 3 to 4N+2 represent the differential gate-source and gate-drain ports of the intrinsic devices. In contrast to [3][4][5], the differential ports used here allow the impedance seen by all intrinsic device ports to vary according to the metal defining the manifold. This permits all the metal in the symmetric test device layout to be algebraically deembedded from measured s-parameters, immediately yielding the device parameters without any compaction, optimisation or iteration.…”

Section: Device Deconstructionmentioning

confidence: 99%

See 1 more Smart Citation

LNA Design Based on an Extracted Single Gate Finger Model

Mahon¹,

Dadello²,

Vun

et al. 2010

2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

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A GaAs low-noise amplifier (LNA) is designed with first-time success using a technique for HEMT modelling which divides the device into intrinsic gate fingers embedded in an analysable metal structure. The gate finger is characterised by de-embedding metallisation from a standard test structure. The device is then re-built, with any geometry or layout that the foundry allows, and modelled by electromagnetic (EM) analysis. This allows techniques such as asymmetric inductive source feedback in an LNA to be modelled without prior fabrication of custom test structures. The 7-13 GHz, self-biased LNA has stateof-the-art noise figure (NF) of 1.25 dB at mid-band, gain of 20.5 ± 0.1 dB with 10 dB input and output matches, 10 dBm P1dB, 14 dBm Psat and 22 dBm OIP3. Excellent agreement is achieved with simulation. In a 3x3 QFN package the measured NF is 1.36 dB and the gain is 20 dB. The first-time design success achieved here validates the modelling and parameter extraction technique.

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Section: Device Deconstructionmentioning

confidence: 99%

Section: Device Deconstructionmentioning

confidence: 99%

LNA Design Based on an Extracted Single Gate Finger Model

Mahon¹,

Dadello²,

Vun

et al. 2010

2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

View full text Add to dashboard Cite

show abstract

“…The determination and subsequent de-embedding of the extrinsic elements is essential to access the performance of the intrinsic FET that is not directly measurable, since the intrinsic section of the FET is experimentally inaccessible. The extrinsic elements are usually determined using "cold" S-parameter measurements (V DS = 0 V, i.e., passive device) [10][11][12][13][14][15][16], passive test structures [13][14][15][16][17], and full-wave electromagnetic simulations [18][19][20][21]. In practice, the "cold" approach is the most used, since it does not require additional dummy structures or detailed information about the FET layout.…”

Section: Introductionmentioning

confidence: 99%

Effects of Gate-Length Scaling on Microwave MOSFET Performance

2017

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This paper focuses on the extraction of an accurate small-signal equivalent circuit for metal-oxide-semiconductor field-effect transistors (MOSFETs). An analytical modeling approach was developed and successfully validated through the comparison between measured and simulated scattering parameters. The extraction of the equivalent circuit elements allowed for the estimation of the intrinsic unity current-gain cutoff frequency, which is a crucial figure of merit for assessing the high-frequency performance. The experimental data show that the cutoff frequency of the tested devices exhibits a nearly ideal scaling behavior with decreasing gate length.

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“…To overcome the computational expense, 'weakly-coupled' approaches have been defined where electromagnetic simulation results (through S-parameters), thermal models (through a thermal impedance matrix), and nonlinear electrothermal transistor models are coupled in the netlist of a circuit simulator. This provides a comprehensive description of the transistor for computationally efficient simulation [6]- [8], [12], [18].…”

Section: Introductionmentioning

confidence: 99%

Multiphysics Modeling of RF and Microwave High-Power Transistors

Aaen¹,

Wood

Bridges³

et al. 2012

IEEE Trans. Microwave Theory Techn.

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Abstract-In this paper, we present a multi-physics approach for the simulation of high-power RF and microwave transistors, in which electromagnetic, thermal, and nonlinear transistor models are linked together within a harmonic-balance circuit simulator. This approach is used to analyze a laterally diffused metal-oxide semiconductor (LDMOS) transistor that has a total gate width of 102 mm and operates at 2.14 GHz. The transistor die is placed in a metal-ceramic package, with bondwire arrays connecting the die to the package leads. The effects of three different gate bondpad layouts on the transistor efficiency are studied. Through plots of the spatial distributions of the drain efficiency and the time-domain currents and voltages across the die, we reveal for the first time unique interactions between the electromagnetic effects of the layout and the microwave behaviour of the large-die LDMOS power field-effect transistor (FET).Index Terms-Global modeling, electrothermal, laterallydiffused metal-oxide-semiconductor (LDMOS) transistor, power field-effect transistor (FET).

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Scalable Nonlinear FET Model Based on a Distributed Parasitic Network Description

Cited by 48 publications

References 34 publications

LNA Design Based on an Extracted Single Gate Finger Model

LNA Design Based on an Extracted Single Gate Finger Model

Effects of Gate-Length Scaling on Microwave MOSFET Performance

Multiphysics Modeling of RF and Microwave High-Power Transistors

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