Scalable inference of decision tree ensembles: Flexible design for CPU-FPGA platforms

Owaida, Muhsen; Zhang, Hantian; Zhang, Ce; Alonso, Gustavo

doi:10.23919/fpl.2017.8056784

Cited by 34 publications

(16 citation statements)

References 15 publications

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“…Storing the ensemble in off-chip memory will significantly diminish the FPGA performance as it does not offer the huge random memory bandwidth and low latency of on-chip memory. In prior work, we have developed two solutions to the problem: partitioning the ensemble into smaller partitions that fit in the FPGA and processing them sequentially on the same FPGA [42], or using a cluster of FPGAs to process very large ensembles [40].…”

Section: Discussionmentioning

confidence: 99%

“…There is a substantial amount of work on using FPGAs for data processing, from databases [56,59,26,32] and cloud systems [14,11,2] to machine-learning [15,23,42,25]. The vast body of existing research has focused on the compute capacity of an FPGA device, ignoring key performance overheads such as the data transfer cost between host and FPGA.…”

Section: Data Processing With Fpgasmentioning

confidence: 99%

“…There is already quite a lot of work on decision trees for FPGAs [17,5,20,20,47,36]. In most cases, it is highly customized to particular applications (e.g., [36]), supports only small decision trees [50] or has been designed for different architectures [42]. Oberg et al [36] presented an FPGA classification pipeline for the Microsoft Kinect depth image pixels.…”

Section: Machine Learning On Fpgasmentioning

confidence: 99%

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Lowering the latency of data processing pipelines through FPGA based hardware acceleration

et al. 2019

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Web search engines often involve a complex pipeline of processing stages including computing, scoring, and ranking potential answers plus returning the sorted results. The latency of such pipelines can be improved by minimizing data movement, making stages faster, and merging stages. The throughput is determined by the stage with the smallest capacity and it can be improved by allocating enough parallel resources to each stage. In this paper we explore the possibility of employing hardware acceleration (an FPGA) as a way to improve the overall performance when computing answers to search queries. With a real use case as a baseline and motivation, we focus on accelerating the scoring function implemented as a decision tree ensemble, a common approach to scoring and classification in search systems. Our solution uses a novel decision tree ensemble implementation on an FPGA to: 1) increase the number of entries that can be scored per unit of time, and 2) provide a compact implementation that can be combined with previous stages. The resulting system, tested in Amazon F1 instances, significantly improves the quality of the search results and improves performance by two orders of magnitude over the existing CPU based solution.

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Section: Discussionmentioning

confidence: 99%

Section: Data Processing With Fpgasmentioning

confidence: 99%

Section: Machine Learning On Fpgasmentioning

confidence: 99%

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Lowering the latency of data processing pipelines through FPGA based hardware acceleration

et al. 2019

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“…In [17], the authors presented an automatic modulation classifier to identify the signal modulation format for electronic applications. In [18], the authors presented a hybrid classification engine using CPU and FPGA shared memory.…”

Section: Related Workmentioning

confidence: 99%

FPGA Acceleration of Tree-based Learning Algorithms

Azmi¹

2020

Adv. sci. technol. eng. syst. j.

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Machine learning classifiers provide many promising solutions for data classification in different disciplines. However, data classification at run time is still a very challenging task for real-time applications. Acceleration of machine-learning hardware solutions is needed to meet the requirements of real-time applications. This paper proposes a new implementation of a machine learning classifier on Field Programmable Gate Arrays (FPGA). The proposed implementation utilizes the MicroBlaze soft-core processor on FPGA and uses the Advanced eXtensible Interface (AXI) bus to integrate the MicroBlaze with hardware peripherals. Experimental results shows that hardware-software co-design is a promising solution as it saves silicon area and provides a flexible configuration of decision tree algorithms at run time.

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“…In [56], hardware acceleration of ensemble classifier based on decision tree is presented and targeted towards embedded applications. In [57], an FPGA based implementation is proposed for ensemble classifier using decision tree, which delivers a multifold improvement in speed. In [58], a graphic processing unit based implementation of decision tree ensembles is presented.…”

Section: Classifier Performance Measuresmentioning

confidence: 99%

Ensemble Classifier Based Spectrum Sensing in Cognitive Radio Networks

Ahmad

2019

Wireless Communications and Mobile Computing

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Spectrum sensing is one of the most important and challenging tasks in cognitive radio. To develop methods of dynamic spectrum access, robust and efficient spectrum sensors are required. For most of these sensors, the main constraints are the lack of information about the primary user's (PU) signal, high computational cost, performance limits in low signal-to-noise ratio (SNR) conditions, and difficulty in finding a detection threshold. This paper proposes a machine learning based novel detection method to overcome these limits. To address the first constraint, detection is achieved using cyclostationary features. The constraints of low SNR, finding detection threshold, and computational cost are addressed by proposing an ensemble classifier. First, a dataset is generated containing different orthogonal frequency-division multiplexing signals at different SNRs. Then, cyclostationary features are extracted using FFT accumulation method. Finally, the proposed ensemble classifier has been trained using the extracted features to detect PU's signal in low SNR conditions. This ensemble classifier is based on decision trees and AdaBoost algorithm. A comparison of the proposed classifier with another machine learning classifier, namely, support vector machine (SVM), is presented, clearly showing that the ensemble classifier outperforms SVM. The results of the simulation also prove the robustness and superior efficiency of the detector proposed in this paper in comparison with a cyclostationary detector without machine learning as well as the classical energy detector.

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Scalable inference of decision tree ensembles: Flexible design for CPU-FPGA platforms

Cited by 34 publications

References 15 publications

Lowering the latency of data processing pipelines through FPGA based hardware acceleration

Lowering the latency of data processing pipelines through FPGA based hardware acceleration

FPGA Acceleration of Tree-based Learning Algorithms

Ensemble Classifier Based Spectrum Sensing in Cognitive Radio Networks

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