Scalable hybrid verification of complex microprocessors

Mneimneh, Maher; Aloul, Fadi; Weaver, Christopher; Chatterjee, S.; Sakallah, Karem A.; Austin, Todd

doi:10.1145/378239.378265

Cited by 18 publications

(13 citation statements)

References 10 publications

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“…Specifically, combinational equivalence checking has been solved using SAT [ 15], and later, several attempts have been made to solve sequential equivalence checking problems using SAT [ 16]. Additionally, SAT has been used for bounded model checking [ 1], microprocessor verification [ 17], and functional vector generation [ 18]. Besides verification, SAT has also been heavily applied in automatic test pattern generation (ATPG) [ 19] and extended to delay fault testing [ 20].…”

Section: Boolean Satisfiabilitymentioning

confidence: 99%

Symmetry in Boolean Satisfiability

Aloul

2010

Symmetry

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This paper reviews recent approaches on how to accelerate Boolean Satisfiability (SAT) search by exploiting symmetries in the problem space. SAT search algorithms traverse an exponentially large search space looking for an assignment that satisfies a set of constraints. The presence of symmetries in the search space induces equivalence classes on the set of truth assignments. The goal is to use symmetries to avoid traversing all assignments by constraining the search to visit a few representative assignments in each equivalence class. This can lead to a significant reduction in search runtime without affecting the completeness of the search.

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Section: Boolean Satisfiabilitymentioning

confidence: 99%

Symmetry in Boolean Satisfiability

Aloul

2010

Symmetry

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“…In a TCO design setting, verification has the opportunity to prioritize its focus: the checker portion of the design demands the highest level of correctness, while the focus for the high-performance portion is on typical-case correctness. The benefit is that the simpler, smaller checker portion of the design lends itself more easily to formal verification, as it is the case for the DIVA architecture of Section II-A [14]. In contrast, the high-performance, complex portion is more suitable to simulation-based verification where simulation tests are mostly focused on the typical, most frequently-used execution scenarios.…”

Section: Synthesis and Verificationmentioning

confidence: 99%

Opportunities and challenges for better than worst-case design

Austin

Bertacco

Blaauw

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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The progressive trend of fabrication technologies towards the nanometer regime has created a number of new physical design challenges for computer architects. Design complexity, uncertainty in environmental and fabrication conditions, and single-event upsets all conspire to compromise system correctness and reliability. Recently, researchers have begun to advocate a new design strategy called Better Than Worst-Case design that couples a complex core component with a simple reliable checker mechanism. By delegating the responsibility for correctness and reliability of the design to the checker, it becomes possible to build provably correct designs that effectively address the challenges of deep submicron design. In this paper, we present the concepts of Better Than Worst-Case design and highlight two exemplary designs: the DIVA checker and Razor logic. We show how this approach to system implementation relaxes design constraints on core components, which reduces the effects of physical design challenges and creates opportunities to optimize performance and power characteristics. We demonstrate the advantages of relaxed design constraints for the core components by applying typical-case optimization (TCO) techniques to an adder circuit. Finally, we discuss the challenges and opportunities posed to CAD tools in the context of Better Than Worst-Case design. In particular, we describe the additional support required for analyzing run-time characteristics of designs and the many opportunities which are created to incorporate typical-case optimizations into synthesis and verification.

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“…Mneimneh et al 86 checker against its ISA. However, in recovery mode, a DIVA checker allows only one instruction in the pipeline at a time, so that mechanisms for avoiding hazards are not triggered, and the checker behaves like a non-pipelined processor, making its verification trivial in that mode.…”

Section: Related Workmentioning

confidence: 99%

Integrating Formal Verification into an Advanced Computer Architecture Course

Velev

2005

IEEE Trans. Educ.

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Abstract. The paper presents a sequence of three projects on design and formal verification of pipelined and superscalar processors. The projects were integrated-by means of lectures and preparatory homework exercises-into an existing advanced computer architecture course taught to both undergraduate and graduate students in a way that required them to have no prior knowledge of formal methods. The first project was on design and formal verification of a 5-stage pipelined DLX processor, implementing the six basic instruction types-register-register-ALU, registerimmediate-ALU, store, load, jump, and branch. The second project was on extending the processor from project one with ALU exceptions, a return-from-exception instruction, and branch prediction; each of the resulting models was formally verified. The third project was on design and formal verification of a dual-issue superscalar version of the DLX from project one. The preparatory homework problems included an exercise on design and formal verification of a staggered ALU, pipelined in the style of the integer ALUs in the Intel Pentium 4. The processors were described in the high-level hardware description language AbsHDL that allows the students to ignore the bit widths of word-level values and the internal implementations of functional units and memories, while focusing entirely on the logic that controls the pipelined or superscalar execution. The formal verification tool flow included the term-level symbolic simulator TLSim, the decision procedure EVC, and an efficient SAT-checker; this tool flow-combined with the same abstraction techniques for defining processors with exceptions and branch prediction, as used in the projects-was applied at Motorola to formally verify a model of the M•CORE processor, and detected bugs. The course went through two iterations-offered at the Georgia Institute of Technology in the summer and fall of 2002-and was taught to 67 students, 25 of whom were undergraduates.

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Scalable hybrid verification of complex microprocessors

Cited by 18 publications

References 10 publications

Symmetry in Boolean Satisfiability

Symmetry in Boolean Satisfiability

Opportunities and challenges for better than worst-case design

Integrating Formal Verification into an Advanced Computer Architecture Course

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