Scalable, high-speed on-chip-based NDN name forwarding using FPGA

Saxena, Divya; Mahar, Suyash; Raychoudhury, Vaskar; Cao, Jiannong

doi:10.1145/3288599.3288613

Cited by 3 publications

(3 citation statements)

References 17 publications

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“…This section verifies the storage consumption of Cuc-FIB and trie structured BST [15] and hash structured BCD [17] . The name set used in the simulation is simulated using random URLs and domain names [23] .…”

Section: Verify the Capacity Of Cuc-fibmentioning

confidence: 84%

“…Taking full advantage of the parallel computing and memory parallel reading capabilities of FPGA, we combined cuckoo searchers into a Cuc-FIB and deployed it on the Xilinx Zynq 7000 FPGA. The search speed can reach 312.5MSPS, which is 76% higher than LNI [12] and 64% higher than BST [15] .…”

Section: Introductionmentioning

confidence: 95%

“…In existing algorithms based on FPGA on-chip memory, the capacity of the name prefix is low, which cannot meet the requirements of NDN networks. For example, binary search tree on-chip FIB (BST) [15] is an algorithm whose search speed can reach 190.48MSPS, but it only verified the 50K scale routing table on board. Compared with the actual NDN routing table, its scale is far from meeting the requirements.…”

Section: Introductionmentioning

confidence: 99%

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High speed and low storage cost name lookup based on field programmable gate array

Lu,

Li,

Diao

2023

Sixth International Conference on Computer Information Science and Application Technology (CISAT 2023)

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As a future network architecture, Named Data Networking (NDN) adopts content name addressing. While decoupling content from location and brings about rapid expansion of routing tables, it makes lookup speed a bottleneck for high-speed data forwarding. Compared to the table lookup method involving CPU, FPGA can significantly improve the table lookup speed through parallel processing. However, there is a huge contradiction between the large scale of NDN routing table and the limited memory space on FPGA chips. Using FPGA external memory can store routing tables, but its reading speed is slow. To address the above issues, a novel cuckoo searcher structure was first designed to reduce FPGA storage space consumption, with a capacity of over 500K in 10Mbit storage space, which is at least 4 times higher than existing BCD algorithms. Then, multiple cuckoo searchers were combined in parallel, called Cuc-FIB, to improve the search speed to 312.5M times per second, which is 64% higher than the existing BST algorithm. Cuc-FIB has been deployed on the Xilinx Zynq 7000 FPGA platform, capable of carrying 500K routing tables and completing 10Gbps, 4-port line speed routing forwarding.

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Section: Verify the Capacity Of Cuc-fibmentioning

confidence: 84%

Section: Introductionmentioning

confidence: 95%

Section: Introductionmentioning

confidence: 99%

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